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rev. 4164e?scr?02/04 features 80c51 core ? 12 or 6 clocks per instruction (x1 and x2 modes) ? 256 bytes scratchpad ram ? dual data pointer ? two 16-bit timer/counters: t0 and t1 t83c5121 with 16 kbytes mask rom t85c5121 with 16 kbytes code ram t89c5121 with 16 kbytes code ram and 16 kbytes eeprom on-chip expanded ram (xram): 256 bytes versatile host serial interface ? full-duplex enhanced uart (euart) with dedicated baud rate generator (brg): most standard speeds up to 230k bits/s at 7.36 mhz ? output enable input ? multiple logic level shifters options (1.8v to v cc ) ? automatic level shifter option multi-protocol smart card interface ? certified with dedicated firmware according to iso 7816, emv2000, gie-cb, gsm 11.12v and whql standards ? asynchronous protocols t = 0 and t = 1 with direct and inverse modes ? baud rate generator supporting all iso7816 speeds up to d = 32/f = 372 ? parity error detection and indication ? automatic character repetition on parity errors ? programmable timeout detection ? card clock stop high or low for card power-down mode ? support synchronous card with c4 and c8 programmable outputs ? card detection and automatic de-activation sequence ? step-up/down converter with programmable voltage output: 5v, 3v ( 8% at 60 ma) and 1.8v (8% at 20 ma) ? direct connection to smart card terminals: short circuit current limitation logic level shifters 4 kv esd protection (mil/std 833 class 3) alternate card support with clk, i/o and rst according to gsm 11.12v standard 2x i/o ports: 6 i/o port1 and 8 i/o port3 2x led outputs with programmable current sources: 2, 4, or 10 ma hardware watchdog reset output includes ? hardware watchdog reset ? power-on reset (por) ? power-fail detector (pfd) 4-level priority interrupt system with 7 sources 7.36 to 16 mhz on-chip oscillator with clock prescaler absolute cpu maximal frequency: 16 mhz in x1 mode, 8mhz in x2 mode idle and power-down modes voltage operation: 2.85v to 5.4v low power consumption ? 8 ma operating current (at 5.4v and 3.68 mhz) ? 150 ma maximum current with smart card power-on (at 16 mhz x1 mode) ?30 a maximum power-down current at 3.0v (without smart card) ?100 a maximum power-down current at 5.4v (without smart card) temperature range ? commercial: 0 to +70 c operating temperature ? industrial: -40 to +85 c operating temperature packages ? ssop24 ? plcc52 8-bit microcontroller with multi- protocol smart card interface t83c5121 t85c5121 t89c5121
2 t8xc5121 4164e?scr?02/04 description t8xc5121 is a high performance cmos rom/cram derivative of the 80c51 cmos single chip 8-bit microcontrollers. t8xc5121 retains the features of the atmel 80c51 with extended rom capacity (16 kbytes), 512 bytes of internal ram, a 4-level interrupt system, two 16-bit timer/counters (t0/t1), a full duplex enhanced uart (euart) with baud rate generator (brg) and an on-chip oscillator. in addition, the t8xc5121 have, a multi protocol smart card interface, a dual data pointer, 2 programmable led current sources (2-4-10 ma) and a hardware watchdog. t89c5121 flash ram version and t85c5121 code ram version can be loaded by in- system programming (isp) software residing in the on-chip rom from a low-cost exter- nal serial eeprom or from r232 interface. t8xc5121 have 2 software-selectable modes of reduced activity for further reduction in power consumption. block diagram figure 1. block diagram notes: 1. alternate function of port 1 2. alternate function of port 3 3. only for the code ram version 4. only for plcc52 timer 0 int ram 256 x8 t0 t1 rxd txd xtal2 xtal1 euart cpu timer 1 int1 ctrl int0 c51 core (2)(2) (2)(2) p1 ib-bus rst vss v cc (1): rom xtal osc xram 256 x8 scib cc8 crst cpres cio cc4 cclk c v cc 6 i/os li crst1 cio1 cclk1 (2) (2) (2) (4) 16k x8 cram 16k x8 (2) (2) p3 8 i/os d v cc voltage reg. (1) (1) (1) (1) (1) (1) led drive direct led0 led1 (2) (2) output : 1-16 clock (3) prescaler x2 watchdog e v cc cvss p2 p0 ea psen ale dc/dc converter level shifters por pfd alternate card brg parallel i/o ports
3 t8xc5121 4164e?scr?02/04 pin description figure 2. t8xc5121 24-pin ssop pinout figure 3. t8xc5121 plcc52 pinout p1.1/cc8 p1.4/cclk p1.0/cio rst p1.5/crst 1 p1.3/cc4 p1.2/cpres xtal1 p3.3/int1/oe p3.2/int0 p3.4/t0 p3.5/cio1/t1 li c v cc cvss v cc e v cc vss p3.0/rxd p3.1/txd 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 p3.6/cclk1/led0 xtal2 p3.7/crst1/led1 d v cc 21 22 26 25 24 23 29 28 27 30 31 5 4 3 2 1 6 52 51 50 49 48 li c v cc vss d v cc p0.1/ad1 p0.0/ad0 p0.2/ad2 p0.5/ad5 p0.6/ad6 p0.3/ad3 p0.4/ad4 p0.7/ad7 p3.6/cclk1/led0 p3.7/crst1/led1 xtal1 p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.2/a10 p2.1/a9 p2.0/a8 p3.0/rxd p3.1/txd p1.5/crst p1.4/cclk p1.3/cc4 p1.2/cpres p1.1/cc8 p1.0/cio ea psen ale p2.3/a11 8 9 10 11 12 13 14 15 16 17 18 46 45 44 43 42 41 40 39 38 37 36 7 47 19 20 32 33 34 35 p3.2/int0 p3.3/int1/oe rst xtal2 p3.5/cio1/t1 p3.4/t0 v cc cvss v cc vss nc nc nc e v cc nc nc nc nc
4 t8xc5121 4164e?scr?02/04 signals all the t8xc5121 signals are detailed in table 1. the port structure is described in section ?port structure description?. table 1. ports description port signal name alternate internal power supply esd type description p1.0 cio cv cc 4 kv i/o smart card interface function card i/o. i/o input/output function p1.0 is a bi-directional i/o port . i reset configuration input . p1.1 cc8 cv cc 4 kv o smart card interface function card contact 8 o output function p1.1 is a push-pull port. i reset configuration input p1.2 cpres v cc 4 kv i smart card interface function card presence i/o input/output function p1.2 is a bi-directional i/o port with internal pull-ups- ( external pull-up configuration can be selected). i reset configuration input (high level due to internal pull-up) p1.3 cc4 cv cc 4 kv o smart card interface function card contact 4 o output function p1.3 is a push-pull port. i reset configuration input (high level due to internal pull-up) p1.4 cclk cv cc 4 kv o smart card interface function card clock i/o input/output function p1.4 is a a push-pull port. o reset configuration output at low level p1.5 crst cv cc 4 kv o smart card interface function card reset i/o input/output function p1.5 is a a push-pull port. o reset configuration output at low level
5 t8xc5121 4164e?scr?02/04 p3.0 rxd ev cc i uart function receive data input i/o input/output function p3.0 is a bi-directional i/o port with internal pull-ups. i reset configuration input (high level) p3.1 txd ev cc o uart function transmit data output oe active at low or high level depending of pmsoen bits in siocon reg. i/o input/output function p3.1 is a bi-directional i/o port with internal pull-ups. z reset configuration high impedance due to pmos switched off p3.2 int0 dv cc i external interrupt 0 int0 input set ie0 in the tcon register. if bit it0 in this register is set, bits ie0 are set by a falling edge on int 0. if bit it0 is cleared, bits ie0 is set by a low level on int0 . i/o input/output function p3.2 is a bi-directional i/o port with internal pull-ups. i timer 0: gate input int0 serves as external run control for timer 0 when selected in tcon register. i reset configuration input (high level) p3.3 int1 oe ev cc i external interrupt 1 int1 input set oeit in isel register, ie1 in the tcon register. if bit it1 in this register is set, bits oeit and ie1 are set by a falling edge on int1 . if bit it1 is cleared, bits oeit and ie1 is set by a low level on int1 i uart function output enable. a low or high level (depending oelev bit in isel register) on this pin disables the pmos transistors of txd (p3.1) and t0 (p3.4). this function can be disabled by software i/o input/output function p3.3 is a bi-directional i/o port with internal pull-ups. i timer 1 function: gate input int1 serves as external run control for timer 1 when selected in tcon register. i reset configuration input (high level) p3.4 t0 ev cc o uart function oe active at low or high level depending of pmsoen bits in siocon reg. table 1. ports description (continued) port signal name alternate internal power supply esd type description
6 t8xc5121 4164e?scr?02/04 i/o input/output function p3.4 is a bi-directional i/o port with internal pull-ups. i timer 0 function: external clock input when timer 0 operates as a counter, a falling edge on the t0 pin increments the count. z reset configuration high impedance due to pmos switched off p3.5 cio1 dv cc i/o alternate card function card i/o i/o input/output function p3.5 is a bi-directional i/o port with internal pull-ups. i timer 1 function: external clock input when timer 1 operates as a counter, a falling edge on the t1 pin increments the count. i reset configuration input (high level due to internal pull-up) p3.6 cclk1 led1 dv cc o alternate card function card clock o led function these pins can be directly connected to the cathode of standard led without external current limiting resistors. the typical current of each output can be programmed by software to 2, 4 or 10 ma (ledcon register). i/o input/output function p3.6 is a led port. i reset configuration input at high level p3.7 crst1 dv cc o alternate card function card reset p3.7 crst1 led0 dv cc o led function these pins can be directly connected to the cathode of standard led without external current limiting resistors. the typical current of each output can be programmed by software to 2, 4 or 10 ma (ledcon register). i/o input/output function p3.7 is a a led port. i reset configuration input at high level table 1. ports description (continued) port signal name alternate internal power supply esd type description
7 t8xc5121 4164e?scr?02/04 rst v cc i/o reset input holding this pin low for 64 oscillator periods while the oscillator is running resets the device. the port pins are driven to their reset conditions when a voltage lower than v il is applied, whether or not the oscillator is running. this pin has an internal pull-up resistor which allows the device to be reset by connecting a capacitor between this pin and vss. asserting rst when the chip is in idle mode or power-down mode returns the chip to normal operation. the output is active for at least 12 oscillator periods when an internal reset occurs. xtal1 v cc i input to the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, its output is connected to this pin. xtal2 v cc o output of the on-chip inverting oscillator amplifier to use the internal oscillator, a crystal/resonator circuit is connected to this pin. if an external oscillator is used, xtal2 may be left unconnected. v cc pwr supply voltage v cc is used to power the internal voltage regulators and internal i/o?s. li pwr dc/dc input li must be tied to v cc through an external coil (typically 4, 7 h) and provide the current for the pump charge of the dc/dc converter. cv cc pwr card supply voltage cv cc is the programmable voltage output for the card interface. it must be connected to an external decoupling capacitor. dv cc pwr digital supply voltage dv cc is used to supply the digital core and internal i/os. it is internally connected to the output of a 3v regulator and must be connected to an external decoupling capacitor. ev cc v cc pwr extra supply voltage ev cc is used to supply the level shifters of uart interface i/o pins. it must be connected to an external decoupling capacitor. this reference voltage is generated internally (automatically or not), or it can be connected to an external voltage reference. cvss gnd dc/dc ground cvss is used to sink high shunt currents from the external coil. vss gnd ground only for plcc52 version table 1. ports description (continued) port signal name alternate internal power supply esd type description
8 t8xc5121 4164e?scr?02/04 p0[7:0] ad[7:0] v cc i/o input/output function port 0 p0 is an 8-bit open-drain bi-directional i/o port. port 0 pins that have 1s written to them float and can be used as high impedance inputs. to avoid any parasitic current consumption, floating p0 inputs must be pulled to v cc or v ss . i/o address/data low mutiplexed address/data lsb for external access p2[7:0] a[15:8] v cc i/o input/output function port 2 p2 is an 8-bit open-drain bi-directional i/o port with internal pull-ups o address high address bus msb for external access p3.6 wr dv cc o write signal write signal asserted during external data memory write operation p3.7 rd dv cc i read signal read signal asserted during external data memory read operation ale v cc o address latch enable output the falling edge of ale strobes the address into external latch psen psen v cc o program strobe enable ea ea v cc i external access enable this pin must be held low to force the device to fetch code from external program memory starting at address 0000h. it is latched during reset and cannot be dynamically changed during operation. table 1. ports description (continued) port signal name alternate internal power supply esd type description
9 t8xc5121 4164e?scr?02/04 port structure description the different ports structures are described as follows. quasi bi-directional output configuration the default port output configuration for standard i/o ports is the quasi bi-directional out- put that is common on the 80c51 and most of its derivatives. this output type can be used as both an input and output without the need to reconfigure the port. this is possi- ble because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the port outputs a logic low state, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi bi-directional out- put that serve different purposes. one of these pull-ups, called the weak pull-up, is turned on whenever the port latch for the pin contains a logic 1. the weak pull-up sources a very small current that will pull the pin high if it is left floating. a second pull- up, called the medium pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the primary source current for a quasi bi-directional pin that is outputting a 1. if a pin that has a logic 1 on it is pulled low by an external device, the medium pull-up turns off, and only the weak pull-up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the medium pull-up and take the voltage on the port pin below its input threshold. figure 4. quasi bi-directional output configuration push-pull output configuration the push-pull output configuration has the same pull-down structure as the quasi bi- directional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. the push-pull port configuration is shown in figure 5. 2 cpu input pin strong weak medium n p p p clock delay port latch data data pmos nmos
10 t8xc5121 4164e?scr?02/04 figure 5. push-pull output configuration led output configuration the input only configuration is shown in figure 6. figure 6. led source current configuration note: the port can be configured in quasi bi-directional mode and the level of current can be programmed by means of ledcon0 and ledcon1 registers before switching the led on by writing a logical 0 in port latch. input pin strong n p port latch data data pmos nmos pin port latch data input data ledx.0 ledx.1 p n n n weak 2 cpu p clock delay pmos strong medium p nmos led1ctrl led2ctrl
11 t8xc5121 4164e?scr?02/04 sfr mapping the special function registers (sfr) of the t8xc5121 belongs to the following categories: c51 core registers: acc, b, dph, dpl, psw, sp i/o port registers: p0, p1, p2, p3 timer 0 registers: tcon, th0, th1, tmod, tl0, tl1 serial i/o port registers: saddr, saden, sbuf, scon, brl, bdrcon power and clock control registers: pcon, ckrl, ckcon0, ckcon1, dcckps interrupt system registers: ie0, ipl0, iph0, ie1,ipl1, iph1, isel watchdog timer 0: wdtrst, wdtprg others: auxr, auxr1, rcon smart card interface: scsr, sccon/scetu0, scisr/scetu1, scier/sciir, sctbuf/scrbuf, scgt0/scwt0, scgt1/scwt1, scicr/scwt2 port configuration: siocon, ledcon
12 t8xc5121 4164e?scr?02/04 reserved table 2. sfr addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ffh f0h b 0000 0000 ledcon xxxx 0000 f7h e8h efh e0h acc 0000 0000 e7h d8h dfh d0h psw 0000 0000 rcon xxxx oxxx d7h c8h cfh c0h c7h b8h ipl0 xxx0 0000 saden 0000 0000 isel 0000 0100 dcckps xxxx xx11 bfh b0h p3 1111 1111 ie1 xxxx 0xxx ipl1 xxxx 0xxx iph1 xxxx 0xxx 0scwt0 * 1000 0000 0scwt1 * 0010 0101 0scwt2 * 0000 0000 iph0 xxx0 0000 b7h 1scgt0 * 0000 1100 1scgt1* 0000 0000 1 scicr * 0000 0000 a8h ie0 0xx0 0000 saddr 0000 0000 0sctbuf* 0000 0000 scsr xxx0 1000 0 sccon * 0x000 0 scisr* 10x0 0000 0 sciir* 0x00 0000 ckcon1 xxxx 0xxx afh 1 scrbuf 0000 000 1scetu0 0111 0100 1scetu1 0xxx 1scier * 0x00 0000 a0h p2 1111 1111 auxr1 xxx xxx0 wdtrst xxxx xxxx wdtprg xxxx x0000 a7h 98h scon xxx0 0000 sbuf xxxx xxxx brl 0000 0000 bdrcon xxx0 0000 9fh 90h p1 xx11 1111 siocon 00xx 0000 ckrl xxxx 111x 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr 00xx xx00 ckcon0 x0x0 x000 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 20 pcon 00xx xx00 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f scrs bit (scsr.0) (*) 0sfr value 1sfr value
13 t8xc5121 4164e?scr?02/04 powermonitor the powermonitor function supervises the evolution of the voltages feeding the micro- controller, and if needed, suspends its activity when the detected value is out of specification. it is guaranteed to start up properly when t8xc5121 is powered up and prevents code execution errors when the power supply becomes lower than the functional threshold. this section describes the functions of the powermonitor. description in order to start up and to properly maintain the microcontroller operation, v dd has to be stabilized in the v dd operating range and the oscillator has to be stabilised with a nomi- nal amplitude compatible with logic threshold. this control is carried out during three phases which are the power-up, normal operation and stop. it complies with the following requirements: it guarantees an operational reset when the microcontroller is powered and a protection if the power supply goes out from the functional range of the microcontroller. figure 7. powermonitor block diagram powermonitor diagram the target of the powermonitor is to survey the power supply in order to detect any volt- age drops which are not in the target specification. this powermonitor block checks two kind of situations that occur: during the power-up condition, when v dd is reaching the product specification during a steady-state condition, when v dd is stable but disturbed by any undesirable voltage drops. figure 8 shows some configurations that can be met by the powermonitor. external power supply dc to dc 3v regulator v dd d v cc c v cc internal reset power-fail detector power-up detector
14 t8xc5121 4164e?scr?02/04 figure 8. power-up and steady-state conditions monitored such device when it is integrated in a microcontroller, forces the cpu in reset mode when v dd reaches a voltage condition which is out of the specification. the thresholds and their functions are: v pfdp : the output voltage of the regulator has reached a minimum functional value at the power-up. the circuit leaves the reset mode. v pfdm : the output voltage of the regulator has reached a low threshold functional value for the microcontroller. an internal reset is set. glitch filtering prevents the system from reset w hen short duration glitches are carried on v dd power supply. the electrical parameters v pfdp , v pfdm , t rise , t fall , t g are specified in the dcparameters section. power-up steady-state condition d v cc reset vpfdp vpfdm t g v cc t rise t fall power-down
15 t8xc5121 4164e?scr?02/04 power monitoring and clock management for applications where power consumption is a critical factor, three power modes are provided: idle mode power-down mode clock management (x2 feature and clock prescaler) 3v regulator modes (pulsed or not pulsed) idle mode an instruction that sets pcon.0 causes the last instruction to be executed before going into the idle mode. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer 0, and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. ale and psen hold at logic high levels. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminat ing the idle mode. the interrupt will be ser- viced, and following reti the next instruction to be executed will be the one following the instruction that put the device into idle. the flag bit gf0 can be used to give an indication if an interrupt occurred during normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service rou- tine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. power-down mode entering power-down mode to save maximum power, a power-down mode can be invoked by software (refer to table 3, pcon register). in power-down mode, the oscillator is stopped and the instruction that invoked power- down mode is the last instruction executed. the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power- down. to properly terminate power-down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. only external interrupts int0 and int1 are useful to exit from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in figure 9. when both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power-down exit will be completed when the first input will be released. in this case the higher priority interrupt service routine is executed. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put it into power-down mode. exit from power-down mode exiting from power-down by external interrupt does not affect the sfrs and the internal ram content.
16 t8xc5121 4164e?scr?02/04 the ports status under power-down is the status which was valid before entering this mode. the int1 interrupt is a multiplexed input (see interrupt paragraph) with cpres (card detection) and rxd (uart rx). so these three inputs can be used to exit from power- down mode. the configurations which must be set are detailed below: rxd input: ? rxen (isel.0) must be set ? ex1 (ie0.2) must be set ? a low level detected during more than 100 microseconds exit from power- down cpres input: ? prsen (isel.1) must be set ? ex1 (ieo.2) must be set ? ea (ie0.7) must be set ? in the int1 interrupt vector, the cplev bit (isel.7) must be inverted and presit bit (isel.5) must be reset. figure 9. power-down exit waveform exiting from power-down by reset redefines all the sfrs, exiting from power-down by external interrupt does no affect the sfrs. exiting from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. sci control prior to entering power-down mode, a de-activation of the smart card system must be performed. led control prior to entering power-down mode, if the led mode output is used, the medium pull-up must be disconnected by setting the ledpd bit in the pcon register (pcon 3). low power mode only in power-down mode, in order to reduce the power consumption, the user can choose to select this low-power mode. the activation reference is the following. first select the low-power mode by setting the lp bit in the auxr register (auxr. 6) the activation of power-down can then be done. int1 int0 xtal1 power-down phase oscillator restart phase active phase active phase
17 t8xc5121 4164e?scr?02/04 reduced emi mode the ale signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. nevertheless, during internal code execution, ale signal is still generated. only in case of plcc52 version, in order to reduce emi, ale signal can be disabled by setting ao bit. the ao bit is located in auxr register at bit location 0 (see table 4). as soon as ao is set, ale is no longer output but remains active during movx and movc instructions and external fetches. during ale disabling, ale pin is weakly pulled high. power modes control registers table 3. pcon register pcon (s:87h) power configuration register reset value = x0xx xx00b 76543210 smod1 smod0 - - ledpd gf0 pd idl bit number bit mnemonic description 7smod1 double baud rate bit set to double the baud rate when timer 1 is used and mode 1, 2 or 3 is selected in scon register. 6smod0 scon select bit when cleared, read/write accesses to scon.7 are to sm0 bit and read/write accesses to scon.6 are to sm1 bit. when set, read/write accesses to scon.7 are to fe bit and read/write accesses to scon.6 are to ovr bit. scon is serial port control register. 5 reserved 4 reserved 3 ledpd led control power-down mode bits when cleaned the i/o pull-up is the standard c51 pull-up control. when set the medium pull-up is disconnected. 2gf0 general-purpose flag 0 one use is to indicate wether an interrupt occurred during normal operation or during idle mode. 1pd power-down mode bit cleared by hardware when an interrupt or reset occurs. set to activate the power-down mode. if idl and pd are both set, pd takes precedence. 0idl idle mode bit cleared by hardware when an interrupt or reset occurs. set to activate the idle mode. if idl and pd are both set, pd takes precedence.
18 t8xc5121 4164e?scr?02/04 table 4. auxr register auxr (s:8eh) auxiliary register reset value = 00xx xx00b 76543210 - lp - - - - extram ao bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6lp low power mode selection clear to select standard mode set to select low consumption mode 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1extram extram select (only for plcc52 version) clear to map xram datas in internal xram memory. set to map xram datas in external xram memory. 0ao ale output bit (only for plcc52 version) clear to restore ale operation during internal fetches. set to disable ale operation during internal fetches.
19 t8xc5121 4164e?scr?02/04 table 5. ie0 register ie0 interrupt enable register (a8h) reset value = 0xx0 0000b 76543210 ea - - es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit clear to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit clear to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0.
20 t8xc5121 4164e?scr?02/04 table 6. isel register isel (s:bah) interrupt enable register reset value = 0x00 0000b 76543210 cplev - rxit presit oelev oeen rxen presen bit number bit mnemonic description 7 cplev card presence detection level this bit indicates which cpres level will bring about an interrupt set this bit to indicate that card presence it will appear if cpres is at high level. clear this bit to indicate that card presence it will appear if cpres is at low level. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5 presit card presence detection interrupt flag set by hardware must be cleared by software 4rxit received data interrupt flag set by hardware must be cleared by software 3 oelev oe/int1 signal active level set this bit to indicate that high level is active. clear this bit to indicate that low level is active. 2oeen oe/int1 interrupt disable bit clear to disable int1 interrupt set to enable int1 interrupt 1 presen card presence detection interrupt enable bit clear to disable the card presence detection interrupt coming from scib. set to enable the card presence detection interrupt coming from scib. 0rxen received data interrupt enable bit clear to disable the rxd interrupt. set to enable the rxd interrupt
21 t8xc5121 4164e?scr?02/04 clock management in order to optimize the power consumption and the execution time needed for a specific task, an internal prescaler feature and a x2 feature have been implemented between the oscillato r and the cpu. functional block diagram figure 10. clock generation diagram if ckrl<>7 then: if ckrl = 7 then: ckrl prescalor factor 71 62 54 46 38 210 112 014 1 2 f osc 1 2(7-ckrl) ckrl = 7 x2 f clk_periph f clk_cpu ckcon0 ckrl f osc 2 x2 0 1 0 1 osc. xtal1 xtal2 f clk cpu C f osc 2 x2 () ----------------- x 1 2 7 ckrl C () ---------------------------------- - = f clk cpu C fosc 2 x2 ------------- - =
22 t8xc5121 4164e?scr?02/04 x2 feature the t8xc5121 core needs only 6 clock periods per machine cycle. this feature called ?x2? provides the following advantages: divides frequency crystals by 2 (cheaper crystals) while keeping same cpu power. saves power consumption while keeping same cpu power (oscillator power saving). saves power consumption by dynamically dividing the operating frequency by 2 in operating and idle modes. increases cpu power by 2 while keeping same crystal frequency. in order to keep the original c51 compatibility, a divider by 2 is inserted between the xtal1 signal and the main clock input of the core (phase generator). this divider may be disabled by software. description the clock for the whole circuit and peripherals is first divided by two before being used by the cpu core and the peripherals. this allows any cyclic ratio to be accepted on xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio from 40 to 60%. as shown in figure 10, x2 bit is validated on the rising edge of the xtal1 2 to avoid glitches when switching from x2 to standard mode. figure 11 shows the switching mode waveforms. figure 11. mode switching waveforms the x2 bit in the ckcon0 register (see table 9) allows to switch (if ckrl=7) from 12 clock periods per instruction to 6 clock periods and vice versa. the t0x2, t1x2, uartx2, and wdx2 bits in the ckcon0 register (see table 9) and scx2 bit in the ckcon1 register (see table 10) allow to switch from standard periph- eral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle). these bits are active only in x2 mode. more information about the x2 mode can be found in the application note "how to take advantage of the x2 features in ts80c51 microcontroller?". xtal1:2 xtal1 cpu clock x2 bit x2 mode std mode std mode f osc
23 t8xc5121 4164e?scr?02/04 clock prescaler before supplying the cpu and the peripherals, the main clock is divided by a factor 2 to 30 to reduce the cpu power consumption. this factor is controlled with the ckrl register. table 7. examples of factors clock control registers clock prescaler register this register is used to reload the clock prescaler of the cpu and peripheral clock. table 8. ckrl register ckrl - clock reload register (97h) reset value = xxxx 111xb xtal (mhz) x2 cpu ckcon0 ckrl value prescaler factor f clk_cpu, f clk_periph (mhz) 16 0 (reset mode) 07h 1 8 16 1 (x2 mode) 07h 1 16 16 1 07h 1 16 16 0 07h 1 8 16 0 06h 2 4 16 1 06h 2 8 76543210 - - - - ckrl ckrl ckrl - bit number bit mnemonic description 7 - 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - 1 ckrl clock reload register prescaler value xxxx 000xb: ckrl=7 and division factor equals 14 xxxx 110xb: ckrl=6 and factor equals 2 xxxx 111xb: ckrl=7 and division factor equals 1 0- reserved the value read from this bit is indeterminate. do not set this bit.
24 t8xc5121 4164e?scr?02/04 table 9. ckcon0 register ckcon0 - clock control register (8fh) reset value = x0x0 x000b 76543210 -wdx2- six2 - t1x2t0x2x2 bit number bit mnemonic description 7- reserved 6wdx2 watchdog clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) cleared to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 5- reserved 4six2 enhanced uart clock (mode 0 and 2) (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 3- reserved 2t1x2 timer 1 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle 1t0x2 timer 0 clock (this control bit is validated when the cpu clock x2 is set; when x2 is low, this bit has no effect) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle 0x2 cpu clock clear to select 12 clock periods per machine cycle (standard mode) for cpu and all the peripherals. set to select 6 clock periods per machine cycle (x2 mode) and to enable the individual peripherals "x2" bits.
25 t8xc5121 4164e?scr?02/04 table 10. ckcon1 register ckcon1 - clock control register (afh) reset value = xxxx 0xxxb 76543210 ----scx2--- bit number bit mnemonic description 7- reserved 6- reserved 5- reserved 4- reserved 3scx2 scib clock clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 2- reserved 1- reserved 0- reserved
26 t8xc5121 4164e?scr?02/04 dc/dc clock the dc/dc block needs a clock with a 50% duty cycle. the frequency must also respect a value between 3.68 mhz and 4 mhz. the first requirement imposes a divider in the clock path and the second constraint is solved with the use of a prescaler. figure 12. functional block diagram clock control register this register is used to reload the clock prescaler of the dc/dc converter clock. table 11. dcckps register dcckps - dc/dc converter reload register (bfh) reset value = xxxx xx11b clock prescaler before supplying the dc/dc bl ock, the oscillator clock is divided by a factor 2 to 5 to adapt the clock needed by the dc/dc converter. this factor is controlled with the dcckps register. the prescaler factor must be chosen to match the requirement range which is 4mhz. table 12. examples of factors 1 f clk_dc/dc f osc f osc 2 to 5 (2 to 5) dcckps address bfh 76543210 - - - - - - dcckps dcckps bit number bit mnemonic description 7:2 - reserved do not use write those bits 1:0 dcckps clock reload register prescaler value 00b: division factor equals 2 01b: division factor equals 3 10b: division factor equals 4 11b: division factor equals 5 (reset value which minimize the consumption) xtal (mhz) dcckps value prescaler factor dc/dc converter clk (mhz) 800h2 4 12 01h 3 4 14.756 02h 4 3.689 16 02h 4 4 20 03h 5 4
27 t8xc5121 4164e?scr?02/04 smart card interface block (scib) introduction the scib provides all signals to directly interface a smart card. compliance with the iso7816, emv?2000, gsm and whql standards has been certified. both synchronous (e.g. memory card) and asynchronous smart cards (e.g. micropro- cessor card) are supported. the component supplies the different voltages requested by the smart card. the power-off sequence is directly managed by the scib. the card presence switch of the smart card connector is used to detect card insertion or card removal. in case of card removal, the scib de-activates the smart card using the de-activation sequence. an interrupt can be generated when a card is inserted or removed. any malfunction is reported to the microcontroller (interrupt + control register). the different operating modes are configured by internal registers. main features support of iso/iec7816 character mode 1 transmit buffer + 1 receive buffer 11 bits etu counter 9 bits guard time counter 24 bits waiting time counter auto-character repetition on error signal detection in transmit mode auto-error signal generation on parity error detection in receive mode power-on and power-off sequence generation manual mode to directly drive the card i/o
28 t8xc5121 4164e?scr?02/04 block diagram the smart card interface block diagram is shown in figure 13. figure 13. scib block diagram functional description the architecture of the smart card interface block is detailed below. barrel shifter it allows the translation between 1 bit serial data and 8 bits parallel data. the barrel function is useful for character repetition since the character is still present in the shifter at the end of the character transmission. this shifter is able to shift the data in both directions and to invert the input or output value in order to manage both direct and inverse iso7816-3 convention. coupled with the barrel shifter there is a parity checker and generator. there are 2 registers connected to this barrel shifter, one for the transmission and one for the reception. they act as buffers to relieve the cpu of timing constraints. scart fsm (smart card asynchronous receiver transmitter finite state machine) this is the core of the design. its purpose is to control the barrel shifter. to sequence correctly the barrel shifter for a reception or a transmission, it uses the signals issued by
29 t8xc5121 4164e?scr?02/04 the different counters. one of the most important counters is the guard time counter that gives time slots corresponding to the character frame. it is enabled only in uart mode. the transition from the receipt mode to the transmit mode is done automatically. priority is given to the transmission. etu counter the etu (elementary timing unit) counter controls the working frequency of the barrel shifter, in fact, it generates the enable signal of the barrel shifter. it is 11 bits wide and there is a special compensation mode activated with the most sig- nificant bit that allows non integer etu value with a working clock equal to the card clock . but the decimal value is limited to a half clock cycle. in fact the bit duration is not fixed. it takes turns in n clock cycles and n-1 clock cycles. the character duration (10 bits) is also equal to 10*(n+1/2) clock cycles. this allows to reach the required precision of the character duration specified by the iso7816 standard. example: f = 372 d = 32 = > etu = 11.625 clock cycles. etu = (etu[10-0] -0.5 * comp)*f with etu[10-0] = 12, comp = 1 (bit 7 of scetu1) to achieve this clock rate we activated the compensation mode and we programmed the etu duration to 12 clock cycles. the result will be a full character duration (10 bits) equal to 11.5 clock cycles. guard time counter the minimum time between the leading edge of the start bit of a character and the lead- ing edge of the start bit of the following character transmitted (guard time) is controlled by one counter. it is 9 bits wide and is incremented at the etu rate. figure 14. guard time counter etu counter scgt1 scgt0 gt[8:0] guard time counter timeout
30 t8xc5121 4164e?scr?02/04 waiting time counter (wt) the wt counter is a 24 bits down counter which can be loaded with the value contained in the scwt2, scwt1, scwt0 registers. its main purpose is time out signal genera- tion. it is 24 bits wide and is decremented at the etu rate. the etu counter acts as a prescaler (see figure 15). when the wt counter timeout, an interrupt is generated and the scib function is locked: reception and emission are disabled. it can be enabled by resetting the macro or reloading the counter. figure 15. waiting time counter the counter is loaded, if wten = 0, during the write of scwt2 register. this counter is available in both uart and manual modes. but the behaviour depends on the selected mode. in manual mode, the wten signal controls the start of the counter (rising edge) and the stop of the counter (falling edge). after a time out of the counter, a falling edge on wten, a reload of scwt2 and a rising edge of wten are necessary to start again the counter and to release the scib macro. the reload of scwt2 transfers all scwt0, scwt1 and scwt2 registers to the wt counter. in uart mode there is an automatic load on the start bit detection. this automatic load is very useful for changing on-the-fly the timeout value since there is a register to hold the load value. this is the case, for example, when in t = 1 a launch is performed on the bwt timeout on the start bit of the last transmitted character. but on the receipt of the first character an other time out value (cwt) must be used . for this, the new load value of the waiting time counter must be loaded with cwt before the transmission of the last character. the reload of scwt[2-0] with the new value occurs with wten = 1. after a time out of the counter in uart mode, the restart is done as in manual mode. the maximum interval between the start leading edge of a character and the start lead- ing edge of the next character is loaded in the scwt2, scwt1, scwt0 registers. in t = 1 mode, the cwt (character waiting time) or the bwt (block waiting time) are loaded in the same registers. the maximum time between two consecutive start bit is wt[23:0] * etu. when used to check bwt according to iso 7816, wt can be set between 971 and 15728651. etu counter wt counter timeout scwt2 scwt1 scwt0 wt[23:0] load wten start bit uart write_scwt2
31 t8xc5121 4164e?scr?02/04 figure 16. t = 0 mode figure 17. t = 1 mode power-on and power-off fsm in this state, the machine applies the signals on the smart card in accordance with iso7816 standard. to be able to power-on the scib, the card presence is mandatory. removal of the smart card will automatically start the power-off sequence as described in figure 18. figure 18. sci deactivation sequence after a card extraction char 1 char 2 < wt > gt bloc 1 char 1 char 2 char n bloc 2 char n+1 char n+2 char n+3 < cwt < bwt < cwt transmission reception v cc rst clk io 8 clock cycles
32 t8xc5121 4164e?scr?02/04 interrupt generator there are several sources of interruption but the scib macro-cell issues only one inter- rupt signal: scib it. figure 19. scib interrupt sources this signal is high level active. one of the sources is able to set up the interrupt signal and this is the read of the smart card interrupt register by the cpu that clears this signal. if during the read of the smart card interrupt register an interrupt occurs, the set of the corresponding bit into the smart card interrupt register and the set of the interrupt signal will be delayed after the read access. registers there are fourteen registers to control the scib macro-cell. they will be described in the section ?dc/dc converter?. some of the register widths are greater than a byte. despite the 8 bits access provided by the biu, the address mapping of this kind of register respects the following rule: the lowest significant byte register is implemented at the higher address. this implementation makes access to these registers easier when using high level pro- gramming language (c,c++). esctbi ciccer escwti escri escpi ecvccer transmit buffer copied to shift register output current out of range output voltage out of range timeout on wt counter complete transmission complete reception parity error detected scib it escti
33 t8xc5121 4164e?scr?02/04 other features clock the ck-iso input must be in the range 1 - 5 mhz according to iso7816. the iso clock diagram and the configuration examples are shown in figure 20. figure 20. clock diagram of the scib block table 13. examples of settings for clocks alternate card a second card named "alternate card" can be controlled. the clock signal cclk1 can be adapted to the xtal frequency. thanks to the clock prescaler which can divide the frequency by 1, 2, 4 or 8. the bits altkps0 and altkps1 in scsr register are used to set this factor. xtal ( mhz) x2 ckcon0 fclk cpu + fclk periph ( mhz) scx2 clk_ iso (1 to 5 mhz) 40 2 0 2 4 1 (mode x2) 4 0 4 81 8 1 4 11.05905.529512.7648 14.7456 0 7.3728 1 3.6864 160814 20 0 10 1 5 1 2 1 clk_cpu clk_iso scib f4_8mhz 0 scx2 ckcon 1.3 reset value = 1 fclk_cpu fclk_periph
34 t8xc5121 4164e?scr?02/04 figure 21. alternate card card presence input the internal pull-up on card presence input can be disconnected in order to reduce the consumption (cpresres, bit 3 in pmod0). in this case, an external resistor (typically 1 m ? ) must be externally tied to v cc . cpres input can generate an interrupt (see interrupt system section). the detection level can be selected. scib reset the scicr register contains a reset bit. if set, this bit generates a reset of the sci and its registers. table 15 shows the scib registers that are reseted and their reset values. table 14. reset values for sci registers sim,sam card alternate card c v cc crst cio cclk f ck_idle 1 0 cclk1 scsr reg. pr3 scsr reg. altkps0,1 scclk1 f ck_idle 1, 2, 4 or 8 p3.6 main card cpres register name scib reset value (binary) scicr 0000 0000b sccon 0x00 0000b scisr 1000 0000b sciir 0x00 0000b scier 0x00 0000b scsr xxx0 1000b sctbuf 0000 0000b scrbuf 0000 0000b scetu1, scetu0 xxx x001b, 0111 0100b (372) scgt1, scgt0 xxxx xxx0b, 0000 1100b (12) scwt2, scwt1, scwt0 0000 0000b, 0010 0101b, 1000 0000b (9600)
35 t8xc5121 4164e?scr?02/04 dc/dc converter the smart card supply voltage (c v cc ) is generated by the integrated dc/dc converter. it is controlled by several registers: the register described in section ?scicr register? controls the cvcc voltage with bits cvcc0, cvcc1 the register described in section ?sccon register?, switches on/off the dc/dc converter with bit cardv cc after the selection of the card voltage (cvcc[1:0]), the carv cc bit is used to switch on the dc\dc converter. the cvccok bit indicates that the card voltage is within the voltage range. it is mandatory to switch off the cv cc before entering in power-down mode.
36 t8xc5121 4164e?scr?02/04 registers description table 15. scicr register scicr (s:b6h, scrs = 1) smart card interface control register reset value = 0000 0000b 76543210 reset carddet cvcc1 cvcc0 uart wten crep conv bit number bit mnemonic description 7 reset reset set this bit to reset the scib and its configuration 6carddet card presence detector sense clear this bit to indicate the card presence detector is opened when no card is inserted (cpres is high). set this bit to indicate the card presence detector is closed when no card is inserted (cpres is low). 5 - 4 cvcc[1:0] card voltage selection: cvcc[ 1] cvcc[ 0] cv cc 000v 0 1 1.8v 10 3v 11 5v 3uart card uart selection clear this bit to use the card i/o bit to drive the card i/o pin. set this bit to use the smart card uart to drive the card i/o pin. also controls the wait time counter as described in section ?waiting time counter (wt)? 2wten wait time counter enable clear this bit to stop the counter and enable the load of the wait time counter hold registers. the hold registers are loaded with scwt0, scwt1 and scwt2 values when scwt2 is written. set this bit to start the wait time counter. the counters stop when it reaches the timeout value. if the uart bit is set, the wait time counter automatically reloads with the hold registers whenever a start bit is sent or received. 1 crep character repetition clear this bit to disable parity error detection and indication on the card i/o pin in receive mode and to disable character repetition in transmit mode. set this bit to enable parity error indication on the card i/o pin in receive mode and to set automatic character repetition when a parity error is indicated in transmit mode. in receive mode, three times error indication is performed and the parity error flag is set after four times parity error detection. in transmit mode, up to three times character repetition is allowed and the parity error flag is set after five times (reset configuration, can be set at 4 using crepset bit in scsr register) consecutive parity error indication. 0conv iso convention clear this bit to use the direct convention: b0 bit (lsb) is sent first, the parity bit is added after b7 bit and a low level on the card i/o pin represents a ?0?. set this bit to use the inverse convention: b7 bit (lsb) is sent first, the parity bit is added after b0 bit and a low level on the card i/o pin represents a ?1?.
37 t8xc5121 4164e?scr?02/04 table 16. sccon register sccon (s:ach, scrs = 0) smart card contacts register reset value = 0x00 0000b 76543210 clk - cardc8 cardc4 cardio cardclk cardrst cardvcc bit number bit mnemonic description 7clk card clock selection clear this bit to use the cardclk bit (cardclk) to drive card clk pin. set this bit to use xtal signal to drive the card clk pin. note: internal synchronization avoids any glitch on the clk pin when switching this bit. 6- reserved the value read from this bit is indeterminate. do not change this bit or write 0. 5 cardc8 card c8 clear this bit to drive a low level on the card c8 pin. set this bit to set a high level on the card c8 pin. 4 cardc4 card c4 clear this bit to drive a low level on the card c4 pin. set this bit to set a high level on the card c4 pin. 3 cardio card i/o when the uart bit is cleared in scicr register, the value of this bit is driven to the card i/o pin. then this pin can be used as a pseudo bi-directional i/o when this bit is set. to be used as an input, this bit must contain a 1. 2cardclk card clk when the clk bit is cleared in sccon register, the value of this bit is driven to the card clk pin. 1 cardrst card rst clear this bit to drive a low level on the card rst pin. set this bit to set a high level on the card rst pin. 0 cardv cc card vcc control clear this bit to desactivate the card interface and set its power-off. the other bits of scc register have no effect while this bit is cleared. set this bit to power-on the card interface. the activation sequence shall be handled by software.
38 t8xc5121 4164e?scr?02/04 table 17. scisr register scisr (s:adh, scrs = 0) smart card uart interface status register reset value = 1000 0000b 76543210 sctbe cardin ciccovf cvccok scwto sctc scrc scpe bit number bit mnemonic description 7sctbe scib transmit buffer empty this bit is set by hardware when the transmit buffer is copied to the transmit shift register of the smart card uart. it is cleared by hardware when sctbuf is written to. 6 cardin card presence status this bit is set when a card is detected (debouncing filter has to be done in software). it is cleared otherwise. 5ciccovf icc overflow on card this bit is set when the current on card is above the limit it shall be cleared by the hardware . 4cvccok card voltage status this bit is set when the output voltage is within the voltage range specified by cvcc field. it is cleared otherwise. 3scwto smart card wait timeout this bit is set by hardware when the smart card wait time counter times out. it shall be cleared by the reload of the counter or by the reset of the scib. 2sctc smart card transmitted character this bit is set by hardware when the smart card uart has transmitted a character. it shall be cleared by software after this register has been read. 1scrc smart card received character this bit is set by hardware when the smart card uart has received a character it is cleared by hardware when scbuf is read. 0scpe smart card parity error this bit is set at the same time as scti or scri if a parity error is detected. it shall be cleared by software after this register has been read.
39 t8xc5121 4164e?scr?02/04 table 18. sciir register sciir (s:aeh, scrs = 0) smart card uart interrupt identification register (read only) reset value = 0x00 0000b 76543210 sctbi - ciccerr cvccerr scwti scti scri scpi bit number bit mnemonic description 7sctbi scib transmit buffer interrupt this bit is set by hardware when the transmit buffer is copied to the transmit shift register of the smart card uart. it is cleared by hardware when this register is read. 6- reserved the value read from this bit is indeterminate. do not change this bit or write 0. 5ciccerr card current status this bit is set when the output current goes out of the current range. it is cleared by hardware when this register is read. 4 cvccerr card voltage status this bit is set when the output voltage goes out of the voltage range specified by cvcc field. it is cleared by hardware when this register is read. 3scwti smart card wait timeout interrupt this bit is set by hardware when the smart card timer 0 times out. it is cleared by hardware when this register is read. 2scti smart card transmit interrupt this bit is set by hardware when the smart card uart completes a character transmission. it is cleared by hardware when this register is read. 1scri smart card receive interrupt this bit is set by hardware when the smart card uart completes a character reception. it is cleared by hardware when this register is read. 0scpi smart card parity error interrupt this bit is set at the same time as scti or scri if a parity error is detected. it is cleared by hardware when this register is read.
40 t8xc5121 4164e?scr?02/04 table 19. scier register scier (s:aeh, scrs = 1) smart card uart interrupt enable register reset value = 0x00 0000b 765 4 3210 esctbi - ciccer ecvccer escwti escti escri escpi bit number bit mnemonic description 7 esctbi smart card uart transmit buffer empty interrupt enable clear this bit to disable the smart card uart transmit buffer empty interrupt. set this bit to enable the smart card uart transmit buffer empty interrupt. 6- reserved the value read from this bit is indeterminate. do not change this bit . 5ciccer card current error interrupt enable clear this bit to disable the card current error interrupt. set this bit to enable the card current error interrupt. 4 ecvccer card voltage error interrupt enable clear this bit to disable the card voltage error interrupt. set this bit to enable the card voltage error interrupt. 3 escwti smart card wait timeout interrupt enable clear this bit to disable the smart card wait timeout interrupt. set this bit to enable the smart card wait timeout interrupt. 2 escti smart card transmit interrupt enable clear this bit to disable the smart card uart transmit interrupt. set this bit to enable the smart card uart transmit interrupt. 1 escri smart card receive interrupt enable clear this bit to disable the smart card uart receive interrupt. set this bit to enable the smart card uart receive interrupt. 0 escpi smart card parity error interrupt enable clear this bit to disable the smart card uart parity error interrupt. set this bit to enable the smart card uart parity error interrupt.
41 t8xc5121 4164e?scr?02/04 table 20. scsr register scsr (s:abh) smart card selection register reset value = xxx0 1000b table 21. sctbuf register sctbuf (s:aa, write-only, scrs = 0) smart card transmit buffer register reset value = 0000 0000b 76543210 - - - crepsel altkps1 altkps0 scclk1 scrs bit number bit mnemonic description 7- reserved 6- reserved 5- reserved 4 crepsel character repetition selection clear this bit to select 5 times repetition before parity error indication set this bit to select 4 times repetition before parity error indication 3-2 altkps1 altkps0 alternate card clock prescaler factor 00altkps = 0: prescaler factor equals 1 01altkps = 1: prescaler factor equals 2 10altkps = 2: prescaler factor equals 4 (reset value) 11altkps = 3: prescaler factor equals 8 1 scclk1 alternate card clock selection set to select the prescaled clock (cclk1) clear to select the standard port configuration (p3.6) 0 scrs smart card register selection the scrs bit selects which set of the scib registers is accessed. 76543210 bit number bit mnemonic description ?? can store a new byte to be transmitted on the i/o pin when sctbe is set. bit ordering on the i/o pin depends on the convention (see scicr register).
42 t8xc5121 4164e?scr?02/04 table 22. scrbuf register scrbuf (s:aa read-only, scrs = 1) smart card receive buffer register reset value = 0000 0000b table 23. scetu1 register scetu1 (s:adh, scrs = 1) smart card etu register 1 reset value = 0xxx x001b 76543210 ???????? bit number bit mnemonic description ?? provides the byte received from the i/o pin when scri is set. bit ordering on the i/o pin depends on the convention (see scicr register). 76543210 comp ???? etu10 etu9 etu8 bit number bit mnemonic description 7comp compensation clear this bit when no time compensation is needed (i.e. when the etu to card clk period ratio is close to an integer with an error less than 1/4 of card clk period). set this bit otherwise and reduce the etu period by 1 card clk cycle for even bits. 6-3 ? reserved the value read from these bits is indeterminate. do not change these bits . 2-0 etu[10:8] etu msb used together with the etu lsb (see scetu0 register).
43 t8xc5121 4164e?scr?02/04 table 24. scetu0 register scetu0 (s:ach, scrs = 1) smart card etu register 0 reset value = 0111 0100b table 25. scgt1 register scgt1 (s:b5h, scrs = 1) smart card transmit guard time register 1 reset value = xxxx xxx0b table 26. scgt0 register scgt0 (s:b4h, scrs = 1) smart card transmit guard time register 0 reset value = 0000 1100b 76543210 etu7 etu6 etu5 etu4 etu3 etu2 etu1 etu0 bit number bit mnemonic description 7-0 etu[7:0] etu lsb the elementary time unit is (etu[10:0] - 0.5*comp)/f, where f is the card clk frequency. according to iso7816, etu[10:0] can be set between 11 and 2047. the default reset value of etu[10:0] is 372 (f = 372, d = 1). 76543210 ??????? gt 8 bit number bit mnemonic description 7-1 ? reserved the value read from these bits is indeterminate. do not change these bits . 0gt8 transmit guard time msb used together with the transmit guard time lsb (see scgt0 register). 76543210 gt7gt6gt5gt4gt3gt2gt1gt0 bit number bit mnemonic description 7-0 gt[7:0] transmit guard time lsb the minimum time between two consecutive start bits in transmit mode is gt[8:0] * etu. according to iso 7816, gt can be set between 11 and 266 (11 to 254+12 etu).
44 t8xc5121 4164e?scr?02/04 table 27. scwt2 register scwt2 (s:b6h, scrs = 0) smart card character/block wait time register 2 reset value = 0000 0000b table 28. scwt1 register scwt1 (s:b5h, scrs = 0) smart card character/block wait time register 1 reset value = 0010 0101b table 29. scwt0 register scwt0 (s:b4h, scrs = 0) smart card character/block wait time register 0 reset value = 1000 0000b 76543210 wt23 wt22 wt21 wt20 wt19 wt18 wt17 wt16 bit number bit mnemonic description 7-0 wt[23:16] wait time byte 2 used together with wt[15:0] (see scwt0 register). 76543210 wt15 wt14 wt13 wt12 wt11 wt10 wt9 wt8 bit number bit mnemonic description 7-0 wt[15:8] wait time byte 1 used together with wt[23:16] and wt[7:0] (see scwt0 register). 76543210 wt7 wt6 wt5 wt4 wt3 wt2 wt1 wt0 bit number bit mnemonic description 7-0 wt[7:0] wait time byte 0 wt[23:0] is the reload value of the wait time counter wtc. the wtc is a general-purpose timer 0. it is using the etu clock and is controlled by the wten bit (see section ?waiting time counter (wt)?). when uart bit of scicr register is set, the wtc is automatically reloaded at each start bit of the uart. it is used to check the maximum time between to consecutive start bits.
45 t8xc5121 4164e?scr?02/04 interrupt system the t8xc5121 has a total of 6 interrupt vectors: four external interrupts (int0 , int1 /oe, cpres, rxd), two timer 0 interrupts (timer 0s 0 and 1), serial port interrupt and smart card interface interrupt. these interrupts are shown in figure 22. figure 22. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the interrupt enable register (see figure 32). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the interrupt priority register (see figure 36) and in the interrupt priority high register (see figure 38). table 30 shows the bit values and priority levels associated with each combination. table 30. priority level bit values 0 3 interrupt polling sequence ti ri tf0 int0 tf1 iph0, ipl0 ie0 0 3 0 3 0 3 0 3 0 3 individual enable global enable low priority interrupt high priority interrupt int1/oe cpres rxd rxen sci rxit cplev ex0 et0 ex1 et1 es esci oeen 0 1 ie1 1 0 0 1 presen 0 1 oelev it1 it0 tcon reg. tcon reg. presit the selection bits except it1 (tcon) are in isel reg. iph1, ipl1 iph.x ip.x interrupt level priority 0 0 0 (lowest) 01 1 10 2 1 1 3 (highest)
46 t8xc5121 4164e?scr?02/04 a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt can?t be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. table 31. interrupt vector addresses int1 interrupt vector the int1 interrupt is multiplexed with the three following inputs: int1/oe : standard 8051 interrupt input rxd: received data on uart cpres: insertion or removall of the main card the setting configurations for each input is detailed below: int1/oe input this interrupt input is active under the following conditions: it must be enabled thanks to oeen bit (isel register) it can be active on a level or falling edge: thanks to it1 bit (tcon register) if level triggering selection is set, the active level 0 or 1 can be selected with oelev bit (isel register) the bit ie1 (tcon register) is set by hardware when external interrupt detected. it is cleared when interrupt is processed. rxd input a second vector interrupt input is the reception of a character. uart rx input can gen- erate an interrupt if enabled with bit rxen (isel.0). the global enable bits ex1 and ea must also be set. then, the bit rxit (isel register) is set by hardware when a low level is detected on p3.0/rxd input. cpres input the third input is the detection of a level change on cpres input (p1.2). this input can generate an interrupt if enabled with pr esen (isel.1), ex1 (ie0.2) and ea (ie0.7) bits. this detection is done according to the level selected with bit cplev (isel.7). then the bit presit (isel.5) is set by hardware when the triggering conditions are met. this bit must be cleared by software. interrupt source vector address ie0 0003h tf0 000bh ie1 & rxit & prit 0013h tf1 001bh ri & ti 0023h sci 0053h
47 t8xc5121 4164e?scr?02/04 table 32. ie0 register reset value = 0xx0 0000b bit addressable 76543210 ea - - es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit clear to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2 ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit clear to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0 ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0.
48 t8xc5121 4164e?scr?02/04 table 33. ie1 register reset value = xxxx 0xxxb 76543210 ----esci--- bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3esci sci interrupt enable clear to disable the sci interrupt. set to enable the sci interrupt. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0- reserved the value read from this bit is indeterminate. do not set this bit.
49 t8xc5121 4164e?scr?02/04 table 34. tcon register tcon (s:88h) timer 0/counter control register reset value = 0000 0000b 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by the hardware when processor vectors to interrupt routine. set by the hardware on timer 0/counter overflow when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer 0/counter 1. set to turn on timer 0/counter 1. 5tf0 timer 0 overflow flag cleared by the hardware when processor vectors to interrupt routine. set by the hardware on timer 0/counter overflow when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer 0/counter 0. set to turn on timer 0/counter 0. 3ie1 interrupt 1 edge flag cleared by the hardware when interrupt is processed if edge-triggered (see it1). set by the hardware when external interrupt is detected on the int 1 pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int 1). set to select falling edge active (edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by the hardware when interrupt is processed if edge-triggered (see it0). set by the hardware when external interrupt is detected on int 0 pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int 0). set to select falling edge active (edge triggered) for external interrupt 0.
50 t8xc5121 4164e?scr?02/04 table 35. isel register reset value = 0000 0100b 76543210 cplev oeit presit rxit oelev oeen presen rxen bit number bit mnemonic description 7 cplev card presence detection level this bit indicates which cpres level will bring about an interrupt set this bit to indicate that card presence it will appear if cpres is at high level. clear this bit to indicate that card presence it will appear if cpres is at low level. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5 presit card presence detection interrupt flag set by hardware must be cleared by software 4rxit received data interrupt flag set by hardware must be cleared by software 3 oelev oe/int1 signal active level set this bit to indicate that high level is active. clear this bit to indicate that low level is active. 2oeen oe/int1 interrupt disable bit clear to disable int1 interrupt set to enable int1 interrupt 1 presen card presence detection interrupt enable bit clear to disable the card presence detection interrupt coming from scib. set to enable the card presence detection interrupt coming from scib. 0rxen received data interrupt enable bit clear to disable the rxd interrupt. set to enable the rxd interrupt (a minimal bit width of 0.1 ms is required to wake up from power-down).
51 t8xc5121 4164e?scr?02/04 table 36. ipl0 register reset value = xxx0 0000b bit addressable 76543210 - - - psl pt1l px1l pt0l px0l bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4 psl serial port priority bit refer to psh for priority level. 3pt1l timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2px1l external interrupt 1 priority bit refer to px1h for priority level. 1pt0l timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0px0l external interrupt 0 priority bit refer to px0h for priority level.
52 t8xc5121 4164e?scr?02/04 table 37. ipl1 register reset value = xxxx 0xxxb bit addressable 76543210 ----pscil--- bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3 pscil reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0- reserved the value read from this bit is indeterminate. do not set this bit.
53 t8xc5121 4164e?scr?02/04 table 38. iph0 register reset value = xxx0 0000b 76543210 - - - psh pt1h px1h pt0h px0h bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4psh serial port priority high bit psh ps priority level 00lowest 01 10 1 1 highest 3pt1h timer 1 overflow interrupt priority high bit pt1h pt1 priority level 00lowest 01 10 1 1 highest 2px1h external interrupt 1 priority high bit px1h px1 priority level 00lowest 01 10 1 1 highest 1pt0h timer 0 overflow interrupt priority high bit pt0h pt0 priority level 00lowest 01 10 1 1 highest 0px0h external interrupt 0 priority high bit px0 hpx0 priority level 00lowest 01 10 1 1 highest
54 t8xc5121 4164e?scr?02/04 table 39. iph1 register reset value = xxxx 0xxxb 76543210 ----pscih--- bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3 pscih sci interrupt priority level most significant bit pscih pscil priority level 00lowest 01 10 1 1 highest priority 2- reserved the value read from this bit is indeterminate. do not set this bit. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0- reserved the value read from this bit is indeterminate. do not set this bit.
55 t8xc5121 4164e?scr?02/04 led ports configuration the current source of the led ports can be adjusted to 3 different values: 2, 4 or 10 ma. the led output is an alternate function of p3.6 an p3.7 and cannot be used while the alternate card function is used. the control register ledcon is detailed below. registers definition table 40. ledcon register reset value = xxxx 0000b 76543210 ----led1[1]led1[0]led0[1]led0[0] bit number bit mnemonic description 7 - 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 - 2 led1[1,0] port led1 configuration: led1[1] led1[0] configuration 0 0 standard c51 port 0 1 2 ma current source when p3.7 is at low level 1 0 4 ma current source when p3.7 is at low level 1 1 10 ma current source when p3.7 is at low level 1 - 0 led0[1,0] port led0 configuration: led0[1] led0[0] configuration 0 0 standard c51 port 0 1 2 ma current source when p3.6 is at low level 1 0 4 ma current source when p3.6 is at low level 1 1 10 ma current source when p3.6 is at low level
56 t8xc5121 4164e?scr?02/04 dual data pointer t8xc5121 contains a dual data pointer accelerating data memory block moves. the standard 80c52 data pointer is a 16-bit value that is used to address off-chip data ram or peripherals. in t8xc5121, the standard 16-bit data pointer is called dptr and located at sfr location 82h and 83h. the second data pointer named dptr1 is located at the same address than the previous one. the dptr select bit (dps / bit0) chooses the active pointer and it is located into the auxr1 register. it should be ser- viced in those sections of code that will periodically be executed within the time required to prevent a wdt reset. the user switches between data pointers by toggling the lsb of the auxr1. the incre- ment (inc) is a solution for this. all dptr-related instructions use the currently selected dptr for any activity. therefore only one instruction is required to switch from a source to a destination address. using the dual data pointer saves code and resources when moves of blocks need to be accomplished. the second data pointer can be used to address the on-chip xram. table 41. dpl register dpl - low byte of dptr1 (82h) reset value = 0000 0000b table 42. dph register dph - high byte of dptr1 (83h) reset value = 0000 0000b 76543210 -------- 76543210 --------
57 t8xc5121 4164e?scr?02/04 table 43. auxr1 register auxr1 - dual pointer selection register (a2h) reset value = xxxx xxx0b 76543210 -------dps bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0dps data pointer 1 clear to select dptr0 as data pointer. set to select dptr1 as data pointer.
58 t8xc5121 4164e?scr?02/04 memory management program memory all the t8xc5121 versions implement 16 kbytes of rom memory, 256 bytes ram and 256 bytes xram. the hardware configuration byte and the split of internal memory spaces depends on the product and is detailed below. rom configuration byte table 44. rom configuration byte hardware register the bljrb depends of the product version: 1: rom mask version 0: eeprom/cram versions this bit defines if, after reset, either the customer rom program or the bootloader pro- gram is executed (for in system programming). program rom lock bits the program lock system protects the on-chip program against software piracy. the t8xc5121 products are delivered with the highest protection level. table 45. t8xc5121 products protection level p = programmed 76543210 -bljrb----- bit number bit mnemonic description 7 reserved 6bljrb bootloader jump ram bit set to configure user code in rom clear to configure bootlader in rom 5-0 reserved program lock bits protection description security level lb1 lb2 3pp ssop24 version: read function is disabled.but checksum control is still enabled plcc52 version: movc instruction executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset. but checksum control is still enabled. external execution is possible.
59 t8xc5121 4164e?scr?02/04 memory mapping in the products versions, the following internal spaces are defined: ram xram cram: 16 kbytes program ram memory rom the specific accesses from/to these memories are: xram: if the bit rps in rcon (described below) is reset, movx instructions address the xram space. cram: if the bit rps in rcon is set, movx instructions address the cram space. table 46. rcon register reset value = xxxx 0xxxb t89c5121 flash rom version three memory blocks are implemented an internal serial eeprom can be loa ded from external with the application program. the rom memory contains the bootloader program. the entry point is located at address f800h. the lower 14k bytes between address c000h and f7ffh is, also, used for the bootloader program. the cram is the application program memory. this memory is mapped in the external ram space. the bit rps in rcon (sfr address 0d1h) is set to map the cram space during movx instructions for first programming or an update, the program can be downloaded in the internal eeprom (and in the cram) from an external device: either an external eeprom if detected or from a host through rs232 serial communication. for this purpose, an in-system programming (isp) is supplied in a bootloader. this bootloader is program masked in rom space. the hardware byte bljrb value is 0. as described on page 7, after reset, the bootloader program is executed. 76543210 -- rps bit number bit mnemonic description 7-4 - reserved the value read from this bit is indeterminate. do not set this bit. 3rps cram space map bit set to map the cram space during movx instructions clear to map the data space during movx. this bit has priority over the extram bit. 2-0 - reserved the value read from this bit is indeterminate. do not set this bit.
60 t8xc5121 4164e?scr?02/04 if a serial communication device (as described above: twi or rs232) is detected, the program download its content in the internal eeprom and in cram. else, the program is internally downloaded from the internal eeprom into the program cram memory (16 kbytes) then, in the two cases, the bootloader executes a long jump at address 0000h which initializes the program counter at the lower address (0000h) of the executable cram. figure 23. cram with rom and eeprom memory mappings t85c121 code ram version two memory blocks are implemented: the rom memory contains the bootloader program. the cram is the application program memory. after reset, the program is downloaded, as described in last paragraph, from either an external eeprom or from an host connected on rs232 serial link into the program cram memory of 16 kbytes. then the program counter is set at address 0000h of the cram space and the program is executed. 16 kbytes 256 bytes 0000h 3fffh cram xram ram rom ffffh f800h c000h entry point bootloader 256 bytes
61 t8xc5121 4164e?scr?02/04 figure 24. cram and rom mappings t83c5121 with mask rom version in this version, the customer program is masked in 16 kbytes rom. the customer program is masked in rom during the final production phase. the rom size will be determined at mask genera tion process depending of the program size. in-system programming the in-system programming (isp) mode is only implemented in the following product versions: eeprom version cram version (the rom product version is masked with the customer program and does not need isp mode) the isp is used to download an application program in the device and to run it. the communication protocols which are implemented are: uart and twi. hardware interface the hardware in relation with the two communication protocols is detailed below: twi protocol serial protocol 16k bytes 0000h 3fffh cram xram ram rom ffffh c000h bootloader f800h entry point 256 bytes 256 bytes
62 t8xc5121 4164e?scr?02/04 figure 25. hardware in relation with the two communication protocols eeprom mapping the 16k bytes eeprom mapping is the following: the three last bytes are reserved respectively: software security byte: address 3ffdh crc bytes: address 3ffeh and 3fffh the use of these bytes is described in the following paragraphs. therefore, the user program must be mapped from 0000h to 3ffch address. eeprom external twi dv cc or ext. v cc (3v) internal eeprom at24c128 v cc v ss dv cc or ext.v cc (3v) a0 = a1 = 0 wp = 0 sda scl twi optional thanks to internal pull-ups dv cc v cc p2.1 p2.0 (a0 = 1,a1 = 0) dvss wp = 1 at 24 c12 8 (default values if not tied) p3.2/int0 uart bootloader address = 01h address = 00h isp software tool sda scl p3.7/crst1 3ffd 3ffe 3fff 0000h reserved address
63 t8xc5121 4164e?scr?02/04 bootloader functional diagram as described in section ?rom configuration byte?, page 58a rom bit bljrb (boot loader jump rom bit) defines which product version is. the bootloader program is mapped in rom space from address c000h up to ffffh and the entry point is located at address f800h. figure 26. bootloader flowchart ack? e2prom at 00 ack? e2prom at 01 error: no twi or serial device detected u character received on uart ? serial communication is detected thanks to time elapsed internal e2prom (at 00) is detected bootloader execution reset rom program execution bljrb = 1 rom bit rom ram+rom ram+rom (pre-prod: application program) f800h versions: rom rom 0000h external e2prom (at 01) is detected (prod) ram,rom,eeprom a serial code is sent on rd pin (p3.7) versions: ssb & p3.7 test twi ext.bypassed? bypassed? ssb & p3.6 test uart bypassed bypassed? program is downloaded from external eeprom into internal an isp software can be used from a pc to program the part. atmel flip software is available program is downloaded from internal eeprom in cram and executed eeprom and cram and executed. rd port = error code = 22h autobaud feature (table52)
64 t8xc5121 4164e?scr?02/04 in-system programming timings the download from the internal eeprom to cram is executed after 4 seconds when operating at 12 mhz frequency. protection mechanisms transfer checks in order to verify that the transfers are free of errors, a crc c heck is implemented dur- ing the download of the program in cram. this test is done at the end of the 16k space programming. as detailed in the next algorithms: in isp mode, if crc test pass, a character y is returned before the crlf characters else a character z is retuned. in download mode, a serial data aa is sent on p3.7 port and cram is not executed. for this purpose, the user program must include in the two last upper bytes (address 3ffeh and 3fffh) the crc of the previous bytes (calculated from the address 0000h to 3fffdh). the following frames are examples incl uding the crc in the two last upper bytes: ff 03 c0 21 04 00 00 08 07 02 08 02 2d db (crc = 2ddbh) ff 03 80 21 02 04 00 0a 03 06 c0 a8 70 01 e3 3d (crc = e33dh) ff 03 c0 21 02 01 00 10 02 06 00 00 00 00 05 06 00 00 76 55 49 ac (crc = 49ach) the crc algorithm is the following : *************************************************************************************************** uint16 compute_crc (uint16 w) { ucharc; w&=(uint16)0x00ff; for (c=(uchar)8;c;c--) { if ((uchar)w&(uchar)1) { w>>=1; w^=(uint16)0x8408; } else w>>=1; return w; data bytes 2 bytes crc hsb lsb address: 3ffe,3fff
65 t8xc5121 4164e?scr?02/04 } void generate_crc_in_frame(void) { checksum_tx=(uint16) ffffh; /* init of the crc variable */ /* loop which compute for each byte (data_byte) to load */ checksum_tx=compute_crc((uint16)data_byte^checksum_tx)^(checksum_tx>>8); /* end of loop */ checksum=~checksum_tx; /* inverts the checksum, so the check will calculate the crc of all the datas and */ /* will find a constant value = f0b8 which is the crc_ref const. of the bootloader */ write_frame(low_byte(checksum)); /* writes the low_byte of the crc first */ write_frame(high_byte(checksum)); /* writes the high_byte */ } *************************************************************************************************** table 47. synthesis of transfer protection mechanisms notes: 1. the transfer of ssb byte is also secured by crc as the crc is computed on all the 16k data. 2. if a bad transfer has occurred in the internal eeprom (crc is bad), as the crc check is finally done at the end of cram programming, application program will not be executed after any reset. read/write protection lock byte in order to protect the content of the internal eeprom, a software security byte (ssb) defines two security levels: level 0: ssb = 0xff: write and read are allowed level 1: ssb = 0xfe: write is disabled level 2: ssb = 0xfc: write and read are disabled this ssb byte is located at address 3ffdh. when the level 2 is set, the command to set level 1 is disabled. the security levels can only be increased. source target check mcu cram crc computed during cram write operation: if error an error code is applied on p3.7 and code execution by ljmp000 is not done. intern. eep mcu this read operation is secured by the write sequence described above mcu intern. eep same protection as in first row above because cram is written in sequence after each page programming of eep ext. eep mcu same as above as data are transferred to eep int and then to cram
66 t8xc5121 4164e?scr?02/04 the only mean to remove the security level 2 is to send a full chip erase command. table 48. synthesis of security mechanisms configuration bits the bootloader tests that twi components are connected as slave components on the twi external bus and later in the algorithm if characters are received on the uart input. this default configuration can be changed, after a first programming, in order: ? to disable new programming in download mode from external serial eeprom to disable isp programming using uart and ? to avoid any conflict with the target hardware on external twi bus or uart. this can be configured with the two higher bits of the ssb byte detailed in the previous paragraph. the bit 7 is used to bypass (if 0) the external twi acknowledge test. the bit 6 is used to bypass (if 0) the uart receipt test. these two bypass modes can be disabled if a level 0 is applied on, respectively, p3.5 and p3.6 pins. this allows to force and use isp even if the device has been configured as programmed device. source function protection internal eeprom write the first protection level of the ssb byte in the internal eeprom protects against isp write command internal eeprom read the second protection level of the ssb byte in the internal eeprom protects against isp read commands cram write the first protection level of the ssb byte in the internal eeprom protects against isp write command in cram cram read the second protection level of the ssb byte in the cram protects against isp read commands data bytes ssb address 3ffd
67 t8xc5121 4164e?scr?02/04 table 49. valid software security byte values uart protocol overview the serial protocol used is described below. physical layer the uart is used to transmit information with the following configuration: character: 8-bit data parity: none stop: 1 bit flow control: none baudrate: autobaud is performed by the bootloader to compute the baudrate chosen by the host. datas and limits as described in section ?transfer checks?, the downloaded program include the crc values in the last two upper bytes of the 16k bytes space. an update of a part of the 16k program cannot be done because the crc value would have to be updated with a value which depends of the actual value of the rest of the program. so the program function of the pc software tool include the individual program com- mands (with 64 data bytes) from address 0000h to address 3fffh. frame description the serial protocol is based on the intel hex-type records. intel hex records consist of ascii characters used to represent hexadecimal values and are summarized below: table 50. intel hex type frame record mark: ? record mark is the start of frame. this field must contain?:?. reclen: ? reclen specifies that the number of bytes of information or data that follow the record type field of the record. load offset: ? load offset specifies the 16-bit starting load offset of the data bytes, therefore this field is used only for program data record (see table 51). ssb values functions fe no bypass and level1 security fc no bypass and level2 security bf,be,bc uart bypass and security levels 7f,7e,7c external twi bypass and security levels 3f,3e,3c uart and ext. twi bypass record mark ?:? reclen load offset record type data or info checksum 1-byte 1-byte = 40h 2-byte 1-byte 64-byte 1-byte
68 t8xc5121 4164e?scr?02/04 record type: ? record type specifies the command type. this field is used to interpret the remaining information within the frame. the encoding for all the current record types are described in table 51. data/info: ? data/info is a 64 bytes length field. it consists of 64 bytes encoded as pairs of hexadecimal digits. the meaning of data depends on the record type. checksum: ? the two?s complement of the 8-bit bytes that result from converting each pair of ascii hexadecimal digits to one byte of binary, and including the reclen field to and including the last byte of the data/info field. therefore, the sum of all the ascii pairs in a record after converting to binary, from the reclen field to and including the checksum field, is zero. notes: 1. a data byte is represented by two ascii characters. 2. when the field load offset is not used, it should be coded as 2 bytes (00h 00h). command description table 51. frame description command command name data[0] data[1] command effect 00h program data program 64 data bytes 01h end of file - - end of file 03h write function 07h 05h 05h 03h 00h 01h 01h full chip erase program ssb level1 program ssb level2 ljmp(data[2],data[3]) (ljmp0000h) 04h display function data[0:1] = start address data [2:3] = end address data[4] = 00h -> display data data[4] = 01h -> blank check data[4] = 03h -> display cram display data 05h read function 07h 0fh 00h 00h read ssb read bootloader version 06h direct load of baud rate hsb lsb not implemented
69 t8xc5121 4164e?scr?02/04 autobaud the isp feature allows a wide range of baud rates in the user application. it is also adaptable to a wide range of oscillator frequencies. this is accomplished by measuring the bit-time of a single bit in a received character. this information is then used to pro- gram the baud rate in terms of timer counts based on the oscillator frequency. the isp feature requires that an initial character (an uppercase u) be sent to the t8xc5121 to establish the baud rate. table show the autobaud capability. protection mechanisms transfer checks table 53. synthesis of the communication protection mechanisms notes: 1. the transfer of ssb byte is also secured by crc as the crc is computed on all the 16k data. 2. if a bad transfer has occurred in the internal eeprom (crc is bad), as the crc check is finally done at the end of cram programming, application program will not be executed after any reset. security table 54. synthesis of the security mechanisms table 52. autobaud performances frequency (mhz) baudrate (khz) 6.176 8 11.0592 12 14.3 14.7456 16 9600 ok ok ok ok ok ok - 19200 ok - ok ok ok ok ok 38400 - ok ok ok ok ok 57600 - - ok - ok ok - 115200 -----ok- source target check uart isp mcu checksum included in commands is tested with calculated checksum: if bad, x echo returned to isp mcu cram crc computed during cram write operation: if error an error code is applied on p3.7. error code?z? is returned to isp. mcu intern. eep same protection as above because cram is written in sequence after each page programming of eep source target case protection uart isp intern. eep read access ssb level 2 must be set (done, if selected, at isp programming or ext eep download) uart isp cram read access ssb level 2 in cram must be set (ssb is downloaded from int eep after reset) uart isp intern. eep partial programming which would not fit with old crc ssb level 1 must be set (done, if selected, at isp programming or ext eep download) then the eep must be, first, erased before reprogramming. programming is done on all the memory space
70 t8xc5121 4164e?scr?02/04 uart isp intern. eep programming ssb level 1 must be set (done, if selected, at isp programming or ext eep donwload) uart isp cram program access ssb level 1 in int eep protects as, first, the int eep is programmed before cram uart isp ssb in eep and cram level 2 to level 1 protected by bootloader uart isp ssb in eep and cram level 1 to level 0 protected by bootloader source target case protection
71 t8xc5121 4164e?scr?02/04 timers/counters introduction the t8xc5121 implements two general-purpose, 16-bit timer 0s/counters. although they are identified as timer 0, timer 1, you can independently configure each to operate in a variety of modes as a timer 0 or as an event counter. when operating as a timer 0, a timer 0/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, a timer 0/counter counts negative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. the timer 0 registers and associated control registers are implemented as addressable special function registers (sfrs). two of the sfrs provide programmable control of the timer 0s as follows: timer 0/counter mode control register (tmod) and timer 0/counter control register (tcon) control respectively timer 0 and timer 1. the various operating modes of each timer 0/counter are described below. timer 0/counter operations for example, a basic operation is timer 0 registers thx and tlx (x = 0, 1) connected in cascade to form a 16-bit timer 0. setting the run control bit (trx) in the tcon register (see figure 55) turns the timer 0 on by allowing the selected input to increment tlx. when tlx overflows it increments thx and when thx overflows it sets the timer 0 over- flow flag (tfx) in the tcon register. setting the trx does not clear the thx and tlx timer 0 registers. timer 0 registers can be accessed to obtain the current count or to enter preset values. they can be read at any time but the trx bit must be cleared to preset their values, otherwise the behavior of the timer 0/counter is unpredictable. the c/tx# control bit selects timer 0 operation or counter operation by selecting the divided-down system clock or the external pin tx as the source for the counted signal. the trx bit must be cleared when changing the operating mode, otherwise the behavior of the timer 0/counter is unpredictable. for timer 0 operation (c/tx# = 0), the time r 0 register counts the divided-down system clock. the timer 0 register incremented once every peripheral cycle. exceptions are the timer 0 2 baud rate and clock- o ut modes in which the timer 0 reg- ister is incremented by the system clock divided by two. for counter operation (c/tx# = 1), the timer 0 register counts the negative transitions on the tx external input pin. the external input is sampled during every s5p2 state. the programmer?s guide describes the notation for the states in a peripheral cycle. when the sample is high in one cycl e and low in the next one, the counter is incremented. the new count value appears in the register during the next s3p1 state after the transition has been detected. since it takes 12 states (24 oscillator periods) to recognize a nega- tive transition, the maximum count rate is 1/24 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full periph- eral cycle.
72 t8xc5121 4164e?scr?02/04 timer 0 timer 0 functions as either a timer 0 or an event counter in four operating modes. figure 27 through figure 30 show the logic configuration of each mode. timer 0 is controlled by the four lower bits of the tmod register (see figure 56) and bits 0, 1, 4 and 5 of the tcon register (see figure 55). the tmod register selects the method of timer 0 gating (gate0), timer 0 or counter operation (t/c0#) and the oper- ating mode (m10 and m00). the tcon register provides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and interrupt type control bit (it0). for normal timer 0 operation (gate0 = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int 0 to control timer 0 operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets the tf0 flag and generates an interrupt request. it is important to stop the timer 0/counter before changing modes. mode 0 (13-bit timer 0) mode 0 configures timer 0 as a 13-bit timer 0 which is set up as an 8-bit timer 0 (th0 register) with a module-32 prescaler implemented with the lower five bits of the tl0 reg- ister (see figure 27). the upper three bits of the tl0 register are indeterminate and should be ignored. prescaler overflow increments the th0 register. figure 27. timer 0/counter x (x = 0 or 1) in mode 0 mode 1 (16-bit timer 0) mode 1 configures timer 0 as a 16-bit timer 0 with the th0 and tl0 registers con- nected in a cascade (see figure 28). the selected input increments the tl0 register. trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer 0 x interrupt request c/tx# tmod reg tlx (5 bits) thx (8 bits) intx# tx fclk_periph
73 t8xc5121 4164e?scr?02/04 figure 28. timer 0/counter x (x = 0 or 1) in mode 1 mode 2 (8-bit timer 0 with auto-reload) mode 2 configures timer 0 as an 8-bit timer 0 (tl0 register) that automatically reloads from the th0 register (see figure 29). tl0 overflow sets the tf0 flag in the tcon reg- ister and reloads tl0 with the contents of th0, which is preset by the software. when the interrupt request is serviced, the hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to the th0 register. figure 29. timer 0/counter x (x = 0 or 1) in mode 2 mode 3 (two 8-bit timer 0s) mode 3 configures timer 0 so that registers tl0 and th0 operate as 8-bit timer 0s (see figure 30). this mode is provided for applications requiring an additional 8-bit timer 0 or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in the tmod register, and tr0 and tf0 in the tcon register in the normal manner. th0 is locked into a timer 0 function (counting f uart ) and takes over use of the timer 1 interrupt (tf1) and run con- trol (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode 3. trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer 0 x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx fclk_periph trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer 0 x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx fclk_periph
74 t8xc5121 4164e?scr?02/04 figure 30. timer 0/counter 0 in mode 3: two 8-bit counters tr0 tcon.4 tf0 tcon.5 int 0 0 1 gate0 tmod.3 overflow timer 0 interrupt request c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrupt request t0 fclk_periph fclk_periph
75 t8xc5121 4164e?scr?02/04 timer 1 timer 1 is identical to timer 0 except for mode 3 which is a hold-count mode. the fol- lowing comments help to understand the differences: timer 1 functions as either a timer 0 or an event counter in the three operating modes. figure 27 through figure 29 show the logical configuration for modes 0, 1, and 2. mode 3 of timer 1 is a hold-count mode. timer 1 is controlled by the four high-order bits of the tmod register (see figure 56) and bits 2, 3, 6 and 7 of the tcon register (see figure 55). the tmod register selects the method of timer 0 gating (gate1), timer 0 or counter operation (c/t1#) and the operating mode (m11 and m01) . the tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and the interrupt type control bit (it1). timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. for normal timer 0 operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr1 allows external pin int 1 to control timer 0 operation. timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag and generates an interrupt request. when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. it is important to stop the timer 0/counter before changing modes. mode 0 (13-bit timer 0) mode 0 configures timer 1 as a 13-bit timer 0, which is set up as an 8-bit timer 0 (th1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 regis- ter (see figure 27). the upper 3 bits of tl1 register are ignored. prescaler overflow increments the th1 register. mode 1 (16-bit timer 0) mode 1 configures timer 1 as a 16-bit timer 0 with th1 and tl1 registers connected in cascade (see figure 28). the selected input increments the tl1 register. mode 2 (8-bit timer 0 with auto-reload) mode 2 configures timer 1 as an 8-bit timer 0 (tl1 register) with automatic reload from the th1 register on overflow (see figure 29) . tl1 overflow sets the tf1 flag in the tcon register and reloads tl1 with the contents of th1, which is preset by the soft- ware. the reload leaves th1 unchanged. mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when the tr1 run control bit is not available i.e., when timer 0 is in mode 3.
76 t8xc5121 4164e?scr?02/04 registers table 55. tcon register tcon (s:88h) - timer 0/counter control register reset value = 0000 0000b 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by the hardware when processor vectors to interrupt routine. set by the hardware on timer 0/counter overflow when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer 0/counter 1. set to turn on timer 0/counter 1. 5tf0 timer 0 overflow flag cleared by the hardware when processor vectors to interrupt routine. set by the hardware on timer 0/counter overflow when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer 0/counter 0. set to turn on timer 0/counter 0. 3ie1 interrupt 1 edge flag cleared by the hardware when interrupt is processed if edge-triggered (see it1). set by the hardware when external interrupt is detected on the int 1 pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int 1). set to select falling edge active (edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by the hardware when interrupt is processed if edge-triggered (see it0). set by the hardware when external interrupt is detected on int 0 pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int 0). set to select falling edge active (edge triggered) for external interrupt 0.
77 t8xc5121 4164e?scr?02/04 reset value = 0000 0000b table 56. tmod register tmod (s:89h) - timer 0/counter mode control registers 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int 1 pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer 0 select bit clear for timer 0 operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m01 operating mode 0 0 mode 0:8-bit timer 0/counter (th1) with 5-bit prescaler (tl1). 0 1 mode 1:16-bit timer 0/counter. 1 0 mode 2:8-bit auto-reload timer 0/counter (tl1). reloaded from th1 at overflow. 1 1 mode 3:timer 1 halted. retains count. 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer 0/counter 0 only while int 0 pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer 0 select bit clear for timer 0 operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0:8-bit timer 0/counter (th0) with 5-bit prescaler (tl0). 0 1 mode 1:16-bit timer 0/counter 1 0 mode 2:8-bit auto-reload timer 0/counter (tl0). reloaded from th0 at overflow. 1 1 mode 3:tl0 is an 8-bit timer 0/counter. th0 is an 8-bit timer 0 using timer 1?s tr0 and tf0 bits. 0m00
78 t8xc5121 4164e?scr?02/04 table 57. th0 register th0 (s:8ch) - timer 0 high byte register. reset value = 0000 0000b table 58. tl0 register tl0 (s:8ah) - timer 0 low byte register. reset value = 0000 0000b table 59. th1 register th1 (s:8dh) - timer 1 high byte register. reset value = 0000 0000b table 60. tl1 register tl1 (s:8bh) - timer 1 low byte register. reset value = 0000 0000b 76543210 bit number bit mnemonic description 7:0 high byte of timer 0 76543210 bit number bit mnemonic description 7:0 low byte of timer 0 76543210 bit number bit mnemonic description 7:0 high byte of timer 1 76543210 bit number bit mnemonic description 7:0 low byte of timer 1
79 t8xc5121 4164e?scr?02/04 serial i/o port the serial i/o port is entirely compatible with the serial i/o port in the 80c52. it provides both synchronous and asynchronous communication modes. it operates as an universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simul- taneously and at different baud rates. serial i/o port includes the following enhancements: framing error detection and automatic address recognition internal baud rate generator figure 31. serial i/o uart port block diagram framing error detection framing bit error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bit in pcon register. figure 32. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register bit is set. software may examine fe bit after each reception to check for data errors. once set, only software or a reset clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when fe feature is enabled, ri rises on stop bit instead of the last data bit (see figure 33 and figure 34). write sbuf ri ti transmitter sbuf receiver ib bus mode 0 transmit receive shift register load sbuf read sbuf interrupt request serial port txd rxd sbuf ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod1 to uart framing error control sm0 to uart mode control set fe bit if stop bit is 0 (framing error)
80 t8xc5121 4164e?scr?02/04 figure 33. uart timings in mode 1 figure 34. uart timings in modes 2 and 3 automatic address recognition the automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (sm2 bit in scon register is set). implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address, the receiver sets ri bit in scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if desired, you may enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e., setting sm2 bit in scon register in mode 0 has no effect). given address each device has an individual address that is specified in saddr register; the saden register is a mask byte that contains don?t care bits (defined by zeros) to form the device?s given address. the don?t care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a giv en address is formed. data byte ri smod0 = x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0 = 1 ri smod0 = 0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0 = 1 fe smod0 = 1
81 t8xc5121 4164e?scr?02/04 to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1100b given0101 01xxb the following is an example of how to use given addresses to address different slaves: slave a:sa ddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:sa ddr1111 0011b saden 1111 1001b given1111 0xx1b slave c:saddr1111 0011b saden 1111 1101b given1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t care bit; for slaves b and c, bit 0 is a 1. to commu- nicate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 0; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves a and b, but not slave c, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don?t care bits, e.g.: saddr0101 0110b s aden1111 1100b s addr or saden1111 111xb the use of don?t care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:sa ddr1111 0001b saden 1111 1010b given1111 1x11b, slave b:sa ddr1111 0011b saden 1111 1001b given1111 1x11b, slave c:saddr = 1111 0010b saden 1111 1101b given1111 1111b for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh.
82 t8xc5121 4164e?scr?02/04 reset addresses on reset, the saddr, saden register are initialized to 00h, i.e. the given and broad- cast addresses are xxxx xxxxb (all don?t care bits). this ensures that the serial port is backwards compatible with the 80c51 microcontrollers that do not support automatic address recognition. uart output configuration voltage level the i/o ports of uart are powered by the ev cc regulator. the voltage of this regulator can be: automatically controlled by the microcontroller which adapt the power supply level versus the oe input voltage level. set at three defined levels (1.8v, 2.3v or 2.8v) these configurations are defined with the evauto and vext0,vext1 bits of siocon register. output enable function the uart outputs (tx, t0) can be controlled by the output enable input. the bits pmosen0 and pmosen1 in siocon register are used to control this output. 0 1 0 1 0 1 pmosen0 pmosen0 pmosen1 oe (p3.3) pmos comman d (active at 1) sfr value 0 1
83 t8xc5121 4164e?scr?02/04 uart control registers table 61. saden register saden slave address mask register (b9h) reset value = 0000 0000b table 62. saddr register saddr slave address register (a9h) reset value = 0000 0000b table 63. sbuf register sbuf serial buffer register (99h) reset value = xxxx xxxxb 76543210 76543210 76543210
84 t8xc5121 4164e?scr?02/04 uart timings the following description will be included in l version: mode selection sm0 and sm1 bits in scon register (see table 67) are used to select a mode among the single synchronous and the three asynchronous modes according to table 64. table 64. serial i/o port mode selection baud rate generator depending on the mode and the source selection, the baud rate can be generated from either the timer 1 or the internal baud rate generator. the timer 1 can be used in modes 1 and 3 while the internal baud rate generator can be used in modes 0, 1 and 3. the addition of the internal baud rate generator allows freeing of the timer 1 for other purposes in the application. it is highly recommended to use the internal baud rate generator as it allows higher and more accurate baud rates than with timer 1. baud rate formulas depend on the modes selected and are given in the following mode sections. timer 1 when using the timer 1, the baud rate is derived from the overflow of the timer. as shown in figure 35 the timer 1 is used in its 8-bit auto-reload mode (detailed in section ?timer 0/counter operations?, page 71). smod1 bit in pcon register allows doubling of the generated baud rate. figure 35. timer 1 baud rate generator block diagram internal baud rate generator when using the internal baud rate generator, the baud rate is derived from the over- flow of the timer. as shown in figure 36, the internal baud rate generator is an 8-bit auto-reload timer feed by the peripheral clock or by the peripheral clock divided by 6 depending on the spd bit in bdrcon register (see table 68). the internal baud rate generator is enabled by setting bbr bit in bdrcon register. smod1 bit in pcon reg- ister allows doubling of the generated baud rate. sm0 sm1 mode description baud rate 0 0 0 synchronous shift register fixed / variable 0 1 1 8-bit uart variable 10 29-bit uart fixed 1 1 3 9-bit uart variable tr1 tcon.6 0 1 gate1 tmod.7 overflow c/t1# tmod.6 tl1 (8 bits) th1 (8 bits) int 1 t1 per clock 6 0 1 smod1 pcon.7 2 t1 clock to serial port
85 t8xc5121 4164e?scr?02/04 figure 36. internal baud rate generator block diagram synchronous mode (mode 0) mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the i/0 capabilities of a device with shift registers. the transmit data (txd) pin outputs a set of eight clock pulses while the receive data (rxd) pin transmits or receives a byte of data. the 8-bit data are transmitted and received least-significant bit (lsb) first. shifts occur at a fixed baud rate. figure 37 shows the serial port block diagram in mode 0. figure 37. serial i/o port block diagram (mode 0) transmission (mode 0) to start a transmission mode 0, write to scon register clearing bits sm0, sm1. as shown in figure 38, writing the byte to transmit to sbuf register starts the transmis- sion. hardware shifts the lsb (d0) onto the rxd pin during the first clock cycle composed of a high level then low level signal on txd. during the eighth clock cycle the msb (d7) is on the rxd pin. then, hardware drives the rxd pin high and asserts ti to indicate the end of the transmission. figure 38. transmission waveforms (mode 0) 0 1 overflow spd bdrcon.1 brg (8 bits) brl (8 bits) per clock 6 ibrg clock brr bdrcon.4 0 1 smod1 pcon.7 2 to serial port brg clock txd rxd sbuf tx sr sbuf rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 mode controller ri scon.0 ti scon.1 per clock baud rate controller write to sbuf txd rxd ti d0 d1 d2 d3 d4 d5 d6 d7
86 t8xc5121 4164e?scr?02/04 reception (mode 0) to start a reception in mode 0, write to scon register clearing sm0, sm1 and ri bits and setting the ren bit. as shown in figure 39, clock is pulsed and the lsb (d0) is sampled on the rxd pin. the d0 bit is then shifted into the shift register. after eight sampling, the msb (d7) is shifted into the shift register, and hardware asserts ri bit to indicate a completed recep- tion. software can then read the received byte from sbuf register. figure 39. reception waveforms (mode 0) baud rate selection (mode 0) in mode 0, baud rate can be either fixed or variable. as shown in figure 40, the selection is done using m0src bit in bdrcon register. figure 41 gives the baud rate calculation formulas for each baud rate source. figure 40. baud rate source selection (mode 0) figure 41. baud rate formulas (mode 0) write to scon txd rxd ri d0 d1 d2 d3 d4 d5 d6 d7 set ren, clear ri 0 1 m0src bdrcon.0 per clock 6 to serial po rt ibrg clock baud_rate = 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f per brl = 256 - 6 (1-spd) ? 32 ? baud_rate 2 smod1 ? f per a. fixed formula b. variable formula baud_rate = 6 f per
87 t8xc5121 4164e?scr?02/04 asynchronous modes (modes 1, 2 and 3) the serial port has one 8-bit and two 9-bit asynchronous modes of operation. figure 42 shows the serial port block diagram in such asynchronous modes. figure 42. serial i/o port block diagram (modes 1, 2 and 3) mode 1 mode 1 is a full-duplex, asynchronous mode. the data frame (see figure 43) consists of 10 bits: one start, eight data bits and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. when a data is received, the stop bit is read in the rb8 bit in scon register. figure 43. data frame format (mode 1) modes 2 and 3 modes 2 and 3 are full-duplex, asynchronous modes. the data frame (see figure 44) consists of 11 bits: one start bit, eight data bits (transmitted and received lsb first), one programmable ninth data bit and one stop bit. serial data is transmitted on the txd pin and received on the rxd pin. on receive, the ninth bit is read from rb8 bit in scon register. on transmit, the ninth data bit is written to tb8 bit in scon register. alterna- tively, you can use the ninth bit as a command/data flag. figure 44. data frame format (modes 2 and 3) transmission (modes 1, 2 and 3) to initiate a transmission, write to scon register, setting sm0 and sm1 bits according to table 64, and setting the ninth bit by writing to tb8 bit. then, writing the byte to be transmitted to sbuf register starts the transmission. reception (modes 1, 2 and 3) to prepare for a reception, write to scon register, setting sm0 and sm1 bits according to table 64, and setting ren bit. the actual reception is then initiated by a detected high-to-low transition on the rxd pin. tb8 scon.3 ibrg clock rxd txd sbuf tx sr rx sr sm1 scon.6 sm0 scon.7 mode decoder m3 m2 m1 m0 ri scon.0 ti scon.1 mode & clock controller sbuf rx rb8 scon.2 sm2 scon.4 t1 clock per clock mode 1 d0 d1 d2 d3 d4 d5 d6 d7 start bit 8-bit data stop bit modes 2 and 3 d0 d1 d2 d3 d4 d5 d6 d8 start bit 9-bit data stop bit d7
88 t8xc5121 4164e?scr?02/04 framing error detection (modes 1, 2 and 3) framing error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bit in pcon register as shown in figure 45. when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two devices. if a valid stop bit is not found, the software sets fe bit in scon register. software may examine fe bit after each reception to check for data errors. once set, only software or a chip reset clear fe bit. subsequently received frames with valid stop bits cannot clear fe bit. when the framing error detection feature is enabled, ri rises on stop bit instead of the last data bit as detailed in figure 35. figure 45. framing error block diagram baud rate selection (modes 1 and 3) in modes 1 and 3, the baud rate is derived either from the timer 1 or the internal baud rate generator and allows different baud rate in reception and transmission. as shown in figure 46 the selection is done using rbck and tbck bits in bdrcon register. figure 47 gives the baud rate calculation formulas for each baud rate source while table 65 details internal baud rate generator configuration for different peripheral clock frequencies and giving baud rates closer to the standard baud rates. figure 46. baud rate source selection (modes 1 and 3) figure 47. baud rate formulas (modes 1 and 3) sm0 1 0 smod0 pcon.6 sm0/fe scon.7 framing error controller fe 0 1 rbck bdrcon.2 t1 clock to serial ibrg clock reception port 0 1 tbck bdrcon.3 t1 clock to serial ibrg clock transmission por t 16 16 baud_rate = 6 (1-spd) ? 32 ? (256 -brl) 2 smod1 ? f per brl = 256 - 6 (1-spd ) ? 32 ? baud_rate 2 smod1 ? f per baud_rate = 6 ? 32 ? (256 -th1) 2 smod1 ? f per th1 = 256 - 192 ? baud_rate 2 smod1 ? f per a. brg formula b. t1 formula
89 t8xc5121 4164e?scr?02/04 table 65. internal baud rate generator value notes: 1. these frequencies are achieved in x1 mode, f per = f osc 2. 2. these frequencies are achieved in x2 mode, f per = f osc . baud rate selection (mode 2) in mode 2, the baud rate can only be programmed to two fixed values: 1/16 or 1/32 of the peripheral clock frequency. as shown in figure 48, the selection is done using smod1 bit in pcon register. figure 49 gives the baud rate calculation formula depending on the selection. figure 48. baud rate generator selection (mode 2) figure 49. baud rate formula (mode 2) baud rate f per = 6 mhz 1 f per = 8 mhz 1 spd smod1 brl error % spd smod1 brl error % 115200-------- 57600 - - - - 1 1 247 3.55 38400 1 1 246 2.34 1 1 243 0.16 19200 1 1 236 2.34 1 1 230 0.16 9600 1 1 217 0.16 1 1 204 0.16 4800 1 1 178 0.16 1 1 152 0.16 baud rate f per = 12 mhz 2 f per = 16 mhz 2 spd smod1 brl error % spd smod1 brl error % 115200 - - - - 1 1 247 3.55 57600 1 1 243 0.16 1 1 239 2.12 38400 1 1 236 2.34 1 1 230 0.16 19200 1 1 217 0.16 1 1 204 0.16 9600 1 1 178 0.16 1 1 152 0.16 4800 1 1 100 0.16 1 1 48 0.16 0 1 smod1 pcon.7 per clock 3 2 3 16 to serial po rt baud_rate = 32 2smod1 ? fper
90 t8xc5121 4164e?scr?02/04 table 66. brl (s:91h) brl register baud rate generator reload register reset value = 0000 0000b 76543210 brl7 brl6 brl5 brl4 brl3 brl2 brl1 brl0 bit number bit mnemonic description 7 - 0 brl7:0 baud rate reload value.
91 t8xc5121 4164e?scr?02/04 reset value = xxx0 0000b table 67. scon register scon (s:98h) serial control registe 76543210 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7 fe framing error bit to select this function, set smod0 bit in pcon register. set by hardware to indicate an invalid stop bit. must be cleared by software. sm0 serial port mode bit 0 to select this function, clear smod0 bit in pcon register. software writes to bits sm0 and sm1 to select the serial port operating mode. refer to sm1 bit for the mode selections. 6sm1 serial port mode bit 1 to select this function, set smod0 bit in pcon register. software writes to bits sm1 and sm0 to select the serial port operating mode. sm0 sm1 mode description baud rate 0 0 0 shift register f osc /12 or variable if src bit in bdrcon is set 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /32 or f osc /64 1 1 3 9-bit uart variable 5sm2 serial port mode bit 2 software writes to bit sm2 to enable and disable the multiprocessor communication and automatic address recognition features. this allows the serial port to differentiate between data and command frames and to recognize slave and broadcast addresses. 4ren receiver enable bit clear to disable reception in mode 1, 2 and 3, and to enable transmission in mode 0. set to enable reception in all modes. 3tb8 transmit bit 8 modes 0 and 1: not used. modes 2 and 3: software writes the ninth data bit to be transmitted to tb8. 2rb8 receiver bit 8 mode 0: not used. mode 1 (sm2 cleared): set or cleared by hardware to reflect the stop bit received. modes 2 and 3 (sm2 set): set or cleared by hardware to reflect the ninth bit received. 1ti transmit interrupt flag set by the transmitter after the last data bit is transmitted. must be cleared by software. 0ri receive interrupt flag set by the receiver after the stop bit of a frame has been received. must be cleared by software.
92 t8xc5121 4164e?scr?02/04 table 68. bdrcon register bdrcon baud rate control register (9bh) reset value = xxx0 0000b 76543210 - - - brr tbck rbck spd src bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit 6- reserved the value read from this bit is indeterminate. do not set this bit 5- reserved the value read from this bit is indeterminate. do not set this bit. 4brr baud rate run control bit clear to stop the baud rate. set to start the baud rate. 3tbck transmission baud rate generator selection bit for first uart clear to select timer 1 for the baud rate generator. set to select internal baud rate generator. 2rbck reception baud rate generator selection bit for first uart clear to select timer 1 for the baud rate generator. set to select internal baud rate generator. 1 spd baud rate speed control bit for first uart clear to select the slow baud rate generator when src = 1. set to select the fast baud rate generator when src = 1. 0src baud rate source select bit in mode 0 for first uart clear to select f osc /12 as the baud rate generator. set to select the internal baud rate generator.
93 t8xc5121 4164e?scr?02/04 table 69. siocon register serial input output configuration register register (91h) reset value = 00xx 0000b 76543210 pmsoen1 pmsoen0 - - cpres res evauto vext0 vext1 bit number bit mnemonic description 7 - 6 pmosen1 pmosen0 output enable function on txd/p3.1 and t0/p3.4: pmsoen1 pmsoen0 0 0 pmos is always off (reset value) 0 1 pmos is always driven according to p3.1 or p3.4 value 1 0 pmos is driven only when oe is high 1 1 pmos is driven only when oe is low 5 - 4 - reserved the value read from this bit is indeterminate. do not set this bit. 3 cpres res card presence pull-up resistor 0 internal pull-up is connected 1 internal pull-up is disconnected 2evauto evcc auto setup set to enable the automatic mode of ev cc regulator clear to disable the automatic mode of ev cc regulator 1 - 0 vext0 vext1 evcc voltage configuration: vext0 vext1 0 0 power-down, ev cc is external (reset value) 01ev cc = 1.8v 10ev cc = 2.3v 11ev cc = 2.7v
94 t8xc5121 4132c?scr?02/04 hardware watchdog timer the wdt is intended as a recovery method in situations where the cpu may be sub- jected to software upset. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is by default disabled from exiting reset. to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will drive an output r eset high pulse at the rst-pin. using the wdt to enable the wdt, user must write 01eh and 0e1h in sequence to the wdtrst, sfr location 0a6h. when wdt is enabled, the user needs to service it by writing to 01eh and 0e1h to wdtrst to avoid wdt overfl ow. the 14-bit counter overflows when it reaches 16383 (3fffh) and this will reset t he device. when wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least every 16383 machine cycle. to reset the wdt the user must write 01eh and 0e1h to wdtrst. wdtrst is a write only register. the wdt counter cannot be read or written. when wdt overflows, it will generate an output reset pulse at the rst-pin. the reset pulse duration is 96 x t clk periph , where t clk periph = 1/f clk periph . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset. to have a more powerful wdt, a 2 7 counter has been added to extend the time-out capability, ranking from 16 ms to 2s @ f osca = 12 mhz. to manage this feature, refer to wdtprg register description, table 70. the wdtprg register should be configured before the wdt activation sequence, and can not be modified until next reset. table 70. wdtrst register wdtrst - watchdog reset register (0a6h) reset value = xxxx xxxxb write only, this sfr is used to reset/enable the wdt by writing 01eh then 0e1h in sequence. 76543210 --------
95 t8xc5121 4132c?scr?02/04 table 71. wdtprg register wdtprg - watchdog timer out register (0a7h) reset value = xxxx x000 wdt during power-down and idle in power-down mode the oscillator stops, which means the wdt also stops. while in power-down mode the user does not need to service the wdt. there are 2 methods of exiting power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power-down mode. when power-down is exited with hardware reset, servicing the wdt should occur as it normally should whenever the t8xc5121 is reset. exiting power-down with an interrupt is significantly different. the interrupt is held low long enough for the oscill ator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service routine. to ensure that the wdt does not overflow within a few states of exiting of powerdown, it is better to reset the wdt just before entering powerdown. in the idle mode, the oscillator cont inues to run. to prevent the wdt from resetting the t8xc5121 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and re-enter idle mode. 76543210 - - - - - s2 s1 s0 bit number bit mnemonic description 7- reserved the value read from this bit is undetermined. do not try to set this bit. 6- 5- 4- 3- 2s2 wdt time-out select bit 2 1s1 wdt time-out select bit 1 0s0 wdt time-out select bit 0 s2 s1 s0 selected time-out 000 (2 14 - 1) machine cycles, 16. 3 ms @ f osca =12 mhz 001 (2 15 - 1) machine cycles, 32.7 ms @ f osca =12 mhz 010 (2 16 - 1) machine cycles, 65. 5 ms @ f osca =12 mhz 011 (2 17 - 1) machine cycles, 131 ms @ f osca =12 mhz 100 (2 18 - 1) machine cycles, 262 ms @ f osca =12 mhz 101 (2 19 - 1) machine cycles, 542 ms @ f osca =12 mhz 110 (2 20 - 1) machine cycles, 1.05 ms @ f osca =12 mhz 111 (2 21 - 1) machine cycles, 2.09 ms @ f osca =12 mhz
96 t8xc5121 4164e?scr?02/04 electrical characteristics absolute maximum ratings dc parameters t a = -40 c to +85 c; v ss = 0 v; v cc = 2.85v to 5.4v; f = 7.36 to 16 mhz table 72. core dc parameters (xtal, rst , p0, p2, ale, psen , ea ) ambiant temperature under bias ......................-25 c to 85 c storage temperature ................................... -65 c to + 150 c voltage on v cc to v ss ........................................-0.5v to + 6.0v voltage on any pin to v ss .......................... -0.5v to v cc + 0.5v note: s tresses at or above those listed under ? absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst .2 v cc + .9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, port 0 and 2 0.45 v i ol = 1.6 ma v oh output high voltage, port 0 and 2 0.9 x v cc vi oh = -40 a di cc digital supply output current 610 mac l = 100 nf dv cc digital supply voltage 2.5 2 .9 3.0 v c l = 100 nf dicc=10ma icc normal power down mode 80 100 a 25c icc pulsed power down mode 20 30 a 50c vcc=3v iccop power supply current i ccop = 0.25 freq (mhz) +4 ma i ccidle = 0.03 freq (mhz) +5 ma v cc = 5.4v and bootloader execution v pfdp power-fail high level threshold 2 .55 v v pfdm power-fail low level threshold 2 .45 v t g power fail glitch time 50 ns t rise, t fall v dd rise and fall time 1 s 600 sec.
97 t8xc5121 4164e?scr?02/04 the operating conditions for i cc tests are the following: figure 50. i cc test condition, active mode figure 51. i cc test condition, idle mode figure 52. i cc test condition, power-down mode ea v cc v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0 v cc plcc52 configuration v cc li rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. v cc plcc52 configuration clock signal v cc li rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. v cc plcc52 configuration v cc li
98 t8xc5121 4164e?scr?02/04 table 73. serial interface dc parameters (p3.0, p3.1, p3.3 and p3.4) table 74. led outputs dc parameters (p3.6 and p3.7) symbol parameter min typ max unit test conditions v il input low voltage -0.5 -0.5 -0.5 0.4 0.5 0.5 v v v ev cc = 1.8v ev cc = 2.3v ev cc = 2.8v external evcc automatic evcc v ih input high voltage 1.4 1.6 2.0 0.7 x ev cc ev cc 2.3 2.8 3.3 ev cc + 0.5 v v v v ev cc = 1.8v ev cc = 2.3v ev cc = 2.8v external ev cc automatic evcc v ol output low voltage 0.4 v i ol = 1.2 ma v oh output high voltage 1.6 1.8 2.2 0.8 x ev cc 1.8 2.3 2.7 ev cc v v v v ev cc = 1.8v i oh = 1 a ev cc = 2.3v ev cc = 2.8v i oh = 10 a external ev cc ei cc extra supply current +3 ma c l = 100 nf ev cc extra supply voltage 1.6 2.1 2.6 1.6 1.7 2.2 2.7 1.8 2.3 2.8 v cc v v v v c l = 100 nf, 1.8v c l = 100 nf, 2.3v c l = 100 nf, 2.8v external ev cc automatic evcc ts sampling time automatic evcc symbol parameter min typ max unit test conditions i ol output low current, p3.6 and p3.7 led modes 1 2 5 2 4 10 4 8 20 ma ma ma 2 ma configuration 4 ma configuration 10 ma configuration (t a = -20 c to +50 c, v cc - v ol = 2v 20%)
99 t8xc5121 4164e?scr?02/04 table 75. smart card 5v interface dc parameters note: 1. capacitor = 10 f, x7r type. maximum esr value is 250 mohm, inductor = 4.7 h. table 76. smart card 3v interface dc parameters note: 1. capacitor = 10 f, x7r type. maximum esr value is 250 mohm, inductor = 4.7 h. table 77. smart card 1.8v interface dc parameters note: 1. capacitor = 10 f, x7r type. maximum esr value is 250 mohm, inductor = 4.7 h. symbol parameter min typ max unit test conditions ci cc card supply current 60 121 105 102 ma v cc = 5.4v v cc = 4v v cc = 2.85v cv cc card supply voltage 4.6 5.4 v cicc = 60 ma cv cc ripple on cvcc 200 mv 0 100 t8xc5121 4164e?scr?02/04 table 78. smart card clock dc parameters (port p1.4) note: 1. the voltage on clk should remain between -0.3v and c v cc + 0.3v during dynamic operation. table 79. alternate card clock dc parameters (port p3.6): 5v tolerant note: 1. the voltage on clk should remain between -0.3v and v cc + 0.3v during dynamic operation. symbol parameter min typ max unit test conditions v ol output low voltage 0(1) 0(1) 0.2 x cv cc 0.4 vi ol = 20 ? (1.8,3 v) i ol = 50 a (5v) i ol output low current 15 ma v oh output high voltage 0.7 x cv cc 0.7 x cv cc cv cc - 0.5 cv cc cv cc cv cc v v v i oh = 20 a (1.8v) i oh = 20 a (3v) i oh = 50 a (5v) i oh output high current 15 ma t r t f rise and fall time 16 22.5 50 ns c in = 30 pf(5v) c in = 30 pf(3v) c in = 30 pf(1.8v) voltage stability -0.25 cv cc -0.5 0.4 x cv cc cv cc + 0.25 vlow level high level symbol parameter min typ max unit test conditions v ol output low voltage 0 (1) 0(1) 0.2 x dv cc 0.5 vi ol = 20 a i ol = -200 a v oh output high voltage 0.7 x dv cc dv cc (1) v i oh = 20 a t r t f rise and fall times 18 ns c in = 30 pf
101 t8xc5121 4164e?scr?02/04 table 80. smart card i/o dc parameters (p1.0) note: 1. the voltage on rst should remain between -0.3v and c v cc + 0.3v during dynamic operation. table 81. alternate card i/o dc parameters (p3.5) : 5v tolerant note: 1. the voltage on i/o should remain between -0.3v and d v cc + 0.3v during dynamic operation. symbol parameter min typ max unit test conditions v il input low voltage 0(1) 0(1) 0.5 0.15 x cv cc vi il = 500 a i il = 20 a i il input low current 500 a v ih input high voltage 0.7 x cv cc cv cc vi ih = -20 a i ih input high current -20 / +20 a v ol output low voltage 0(1) 0.4 0.4 0.3 v i ol = 1 a (5v) i ol = 1 ma (3v) i ol = 1 ma (1.8v) i ol output low current 15 ma v oh output high voltage 0.8 x cv cc cv cc (1) v i oh = 20 a (5v,3v,1.8v) i oh output high current 15 ma t r t f rise and fall times 0.8 sc in = 30 pf output symbol parameter min typ max unit test conditions v il input low voltage -0.3 0.2 x dv cc vi il = 1 ma v ih input high voltage 0.7 x dv cc dv cc + 0.3 v i ih = -20 a v ol output low voltage 0(1) 0.3 v i ol = 1000 a v oh output high voltage 0.7 x dv cc dv cc (1) v i oh = 20 a t r t f rise and fall delays 1 sc in = 30 pf
102 t8xc5121 4164e?scr?02/04 table 82. smart card rst, cc4, cc8, dc parameters (port p1.5, p1.3, p1.1) note: 1. the voltage on rst should remain between -0.3v and c v cc + 0.3v during dynamic operation. table 83. alternate card rst dc parameters (port p3.7) : 5v tolerant note: 1. the voltage on rst should remain between -0.3v and d v cc + 0.3v during dynamic operation. table 84. card presence dc parameters (p1.2) symbol parameter min typ max unit test conditions v ol output low voltage 0(1) 0(1) 0.12 x cv cc 0.4 v i ol = 20 ? i ol = 50 ? i ol output low current 15 ma v oh output high voltage cv cc - 0.5 0.8 x cv cc cv cc cv cc (1) vi oh = 50 ? i oh = 20 ? i oh output high current 15 ma t r t f rise and fall delays 0.8 sc in = 30 pf voltage stability -0.25 cv cc -0.5 0.4 x cv cc cv cc + 0.25 low level high level symbol parameter min typ max unit test conditions v ol output low voltage 0 (1) 0.2 x dv cc vi ol = 200 ? v oh output high voltage 0.8 x dv cc 0.8 x dv cc dv cc (1) dv cc v i oh = 20 ? ( 1.8v) i oh = 200 ? ( 3v) t r t f rise and fall delays 400 sc in = 30 pf symbol parameter min typ max unit test conditions i ol1 cpres weak pull- up output current 31025 a p1.2 = 1, short to v ss (internal pull-up enabled)
103 t8xc5121 4164e?scr?02/04 typical application figure 53. typical application diagram notes: 1. c4 and c5 must be placed near ic and have low esr (<250m ? ) 2. straight and short connections avoid any loop between: - cvss and v ss - c v cc and c4, c5 3. v cc connection of the master card must be placed as follows: 4. current is limited to 10 ma. 5. cclk should be routed far from crst, cio, cc4, cc8 and surrounded with ground tracks. 10f v cc rxd txd v cc txd rxd xtal1 xtal2 li cv cc cpres crst cclk cc4 cc8 cio cv cc (1)(2)(3) v ss i/o c8 c4 clk (5) rst 4.7 f v ss oe rts v ss v ss int1/oe t0 v ss 100nf v ss dv cc ev cc 100nf v ss dv cc (4) led0 led1 c1 c2 c3 c4 l1 4.7 h v ss v ss master card y1 i/o rst clk alternate card cio1 crst1 cclk1 v cc 1mohm (optional resistor) or v cc serial interface cvss 22 pf v ss vcc positive detection mode resonator or quartz with standard capacitors 100nf c5 c6 c v cc to card v cc cvss c4, c5
104 t8xc5121 4164e?scr?02/04 ordering information note: 1. contact atmel for availability. part number code memory size (bytes) supply voltage temperature range max frequency package packing product marking t83c5121xxx- icsil 16k rom 2.85 - 5.4v industrial 16 mhz ssop24 stick 83c5121-il t83c5121xxx- icril 16k rom 2.85 - 5.4v industrial 16 mhz ssop24 tape & reel 83c5121-il t83c5121xxx- s3sil 16k rom 2.85 - 5.4v industrial 16 mhz plcc52 (1) stick 83c5121-il t83c5121xxx- s3ril 16k rom 2.85 - 5.4v industrial 16 mhz plcc52 (1) tape & reel 83c5121-il t85c5121-icsil 16k ram 2.85 - 5.4v industrial 16 mhz ssop24 stick 85c5121-el t85c5121-icril 16k ram 2.85 - 5.4v industrial 16 mhz ssop24 tape & reel 85c5121-il t85c5121-s3sil 16k ram 2.85 - 5.4v industrial 16 mhz plcc52 stick 85c5121-el t85c5121-s3ril 16k ram 2.85 - 5.4v industrial 16 mhz plcc52 tape & reel 85c5121-il t89c5121-icsil 16k flash ram 2.85 - 5.4v industrial 16 mhz ssop24 stick 89c5121-il T89C5121-ICRIL 16k flash ram 2.85 - 5.4v industrial 16 mhz ssop24 tape & reel 89c5121-il
105 t8xc5121 4164e?scr?02/04 package drawings ssop24
106 t8xc5121 4164e?scr?02/04 plcc52
107 t8xc5121 4164e?scr?02/04 datasheet change log for t8xc5121 changes from 4164b - 06/02 to 4164c - 07/03 1. ports description update. 2. added bootloader autobaud table. 3. modified i cc test conditions figure 51. 4. added i ccop power supply current characteristics. 5. added i cco pulsed power down mode current characteristics. 6. modified smart card characteristics : v cc /cv cc mixed. changes from 4164c - 07/03 to 4164d - 12/03 1. changed value of emv to emv2000. section ?features?, page 1. changes from 4164d - 12/03 to 4164e - 01/04 1. dvcc min/max values changed, page 96. 2. alternate card pads are 5v tolerant, page 99.
i t8xc5121 4164d?scr?12/03 table of contents features ................................................................................................. 1 description ............................................................................................ 2 block diagram ....................................................................................... 2 pin description ..................................................................................... 3 signals ...................................................................................................................4 port structure description......................................................................................9 sfr mapping ....................................................................................... 11 powermonitor ...................................................................................... 13 description.......................................................................................................... 13 powermonitor diagram ....................................................................................... 13 power monitoring and clock management ...................................... 15 idle mode ............................................................................................................ 15 power-down mode.............................................................................................. 15 clock management ............................................................................. 21 functional block diagram................................................................................... 21 x2 feature ...........................................................................................................22 clock prescaler....................................................................................................23 clock control registers ...................................................................................... 23 dc/dc clock ........................................................................................ 26 clock control register........................................................................................ 26 clock prescaler................................................................................................... 26 smart card interface block (scib) .................................................... 27 introduction ......................................................................................................... 27 main features..................................................................................................... 27 block diagram .....................................................................................................28 functional description ........................................................................................ 28 other features.....................................................................................................33 dc/dc converter.................................................................................................35 registers description...........................................................................................36 interrupt system ................................................................................. 45 int1 interrupt vector .......................................................................................... 46 led ports configuration .................................................................... 55 registers definition............................................................................................. 55 dual data pointer ................................................................................ 56
ii t8xc5121 4164d?scr?12/03 memory management ......................................................................... 58 program memory ................................................................................................ 58 in-system programming ..................................................................................... 61 protection mechanisms ...................................................................................... 64 autobaud ............................................................................................................ 69 protection mechanisms ...................................................................................... 69 timers/counters ................................................................................. 71 introduction ......................................................................................................... 71 timer 0/counter operations ............................................................................... 71 timer 0.................................................................................................................72 timer 1.................................................................................................................75 registers............................................................................................................. 76 serial i/o port ...................................................................................... 79 framing error detection ..................................................................................... 79 automatic address recognition.......................................................................... 80 uart output configuration................................................................................ 82 uart control registers ..................................................................................... 83 uart timings ..................................................................................... 84 mode selection ................................................................................................... 84 baud rate generator.......................................................................................... 84 asynchronous modes (modes 1, 2 and 3) ...........................................................87 hardware watchdog timer ................................................................ 94 using the wdt ................................................................................................... 94 wdt during power-down and idle...................................................................... 95 electrical characteristics ................................................................... 96 absolute maximum ratings ............................................................................... 96 dc parameters ................................................................................................... 96 typical application ........................................................................... 103 ordering information........................................................................ 104 package drawings ............................................................................ 105 ssop24............................................................................................................ 105 plcc52 .............................................................................................................106 datasheet change log for t8xc5121 ............................................. 107 changes from 4164b -06/02 to 4164c - 07/03................................................. 107 changes from 4164c - 07/03 to 4164d - 12/03................................................ 107 changes from 4164d - 12/03 to 4164e - 01/04................................................ 107
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